Deterministic Constant-Amortized-RMR Abortable Mutex for CC and DSM

The abortable mutual exclusion problem, proposed by Scott and Scherer in response to the needs in real-time systems and databases, is a variant of mutual exclusion that allows processes to abort from their attempt to acquire the lock. Worst-case constant remote memory reference algorithms for mutual exclusion using hardware instructions such as Fetch&Add or Fetch&Store have long existed for both cache coherent (CC) and distributed shared memory multiprocessors, but no such algorithms are known for abortable mutual exclusion. Even relaxing the worst-case requirement to amortized, algorithms are only known for the CC model. In this article, we improve this state of the art by designing a deterministic algorithm that uses Fetch&Store to achieve amortized O (1) remote memory reference in both the CC and distributed shared memory models. Our algorithm supports Fast Abort (a process aborts within six steps of receiving the abort signal) and has the following additional desirable properties: it supports an arbitrary number of processes of arbitrary names, requires only O (1) space per process, and satisfies a novel fairness condition that we call Airline FCFS . Our algorithm is short with fewer than a dozen lines of code.

SmartIO

The large variety of compute-heavy and data-driven applications accelerate the need for a distributed I/O solution that enables cost-effective scaling of resources between networked hosts. For example, in a cluster system, different machines may have various devices available at different times, but moving workloads to remote units over the network is often costly and introduces large overheads compared to accessing local resources. To facilitate I/O disaggregation and device sharing among hosts connected using Peripheral Component Interconnect Express (PCIe) non-transparent bridges, we present SmartIO. NVMes, GPUs, network adapters, or any other standard PCIe device may be borrowed and accessed directly, as if they were local to the remote machines. We provide capabilities beyond existing disaggregation solutions by combining traditional I/O with distributed shared-memory functionality, allowing devices to become part of the same global address space as cluster applications. Software is entirely removed from the data path, and simultaneous sharing of a device among application processes running on remote hosts is enabled. Our experimental results show that I/O devices can be shared with remote hosts, achieving native PCIe performance. Thus, compared to existing device distribution mechanisms, SmartIO provides more efficient, low-cost resource sharing, increasing the overall system performance.

Prospects of real time tsunami inundation estimates with TsunAWI - Studies in the LEXIS project

<p>Based on the shallow water equations,the tsunami wave propagation in the deep ocean and an assessment of the wave height at the coast can easily be simulated online during an event. To simulate the estimated inundation, however, poses higher demands on model physics and mesh resolution. Whereas in the deep ocean, a simple balance between pressure gradient force and acceleration is sufficient for first estimates of the wave propagation, additional nonlinear factors like bottom friction and momentum advection gain importance close to the coast. For a seamless simulation of the transition from wave propagation to inundation, the finite element model TsunAWI has been developed as part of the efforts within the GITEWS project (German Indonesian Tsunami Early Warning System) and in the meantime, the code has evolved considerably with applications in several projects. The triangular mesh approach allows for large freedom in the resolution of coastline and bathymetric features, however is also numerically demanding. In the ongoing EU-project LEXIS (Large-scale Execution for Industry & Society), the simulation of earthquake and tsunami events is one of the pilot study cases and on the tsunami side puts focus on the optimization of TsunAWI on modern HPC architectures. Targeting FPGAs, an accelerator for TsunAWI is being designed. It relies on a software-distributed shared memory (S-DSM) allowing sharing of the memory between distributed nodes and the accelerator(s), and is showing that TsunAWI optimisations, namely single precision and unstructured mesh traversal, are key elements to reach high performance and efficiency. For HPC systems, an MPI parallelization was implemented, based on domain decomposition. The MPI parallel code shows good scaling, making high resolution simulations feasible during an event. The developments are evaluated in simulations of tsunami inundation in hypothetical and real events in Indonesia and Chile. It turns out that the optimized approach allows for improved fast estimates of the tsunami impact in the application cases.</p>