CALVIS: Educational Tool in Learning Intel x86-32 Instruction Set Architecture

Theory and Practice of Computation ◽

10.1142/9789813234079_0005 ◽

2017 ◽

Author(s):

Jennica Grace Alcalde ◽

Goodwin Chua ◽

Ivan Marlowe Demabildo ◽

Marielle Ashley Ong ◽

Roger Luis Uy

Keyword(s):

Educational Tool ◽

Instruction Set ◽

Instruction Set Architecture

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Application-Specific Instruction Set Architecture for an Ultralight Hardware Security Module

2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) ◽

10.1109/host45689.2020.9300292 ◽

2020 ◽

Author(s):

Ahmed A. Ayoub ◽

Mark D. Aagaard

Keyword(s):

Hardware Security ◽

Instruction Set ◽

Instruction Set Architecture ◽

Specific Instruction ◽

Security Module ◽

Application Specific

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Model checking to find vulnerabilities in an instruction set architecture

2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) ◽

10.1109/hst.2016.7495566 ◽

2016 ◽

Author(s):

Chris Bradfield ◽

Cynthia Sturton

Keyword(s):

Model Checking ◽

Instruction Set ◽

Instruction Set Architecture

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Instruction-set architecture exploration strategies for deeply clustered VLIW ASIPs

2013 2nd Mediterranean Conference on Embedded Computing (MECO) ◽

10.1109/meco.2013.6601361 ◽

2013 ◽

Author(s):

Roel Jordans ◽

Rosilde Corvino ◽

Lech Jozwiak ◽

Henk Corporaal

Keyword(s):

Instruction Set ◽

Instruction Set Architecture ◽

Architecture Exploration

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A reversible instruction set architecture and algorithms

Proceedings Workshop on Physics and Computation. PhysComp '94 ◽

10.1109/phycmp.1994.363690 ◽

2002 ◽

Author(s):

J. Storrs Hall

Keyword(s):

Instruction Set ◽

Instruction Set Architecture

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Life-Cycle Cost Analysis of Instruction-Set Architecture Standardization for Military Computer Systems

Computer ◽

10.1109/mc.1979.1658693 ◽

1979 ◽

Vol 12 (4) ◽

pp. 35-47 ◽

Author(s):

Stone

Keyword(s):

Cost Analysis ◽

Life Cycle Cost ◽

Computer Systems ◽

Life Cycle Cost Analysis ◽

Instruction Set ◽

Instruction Set Architecture

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Switching activity minimization by efficient instruction set architecture design

The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002. ◽

10.1109/mwscas.2002.1186904 ◽

2003 ◽

Author(s):

V. Ramakrishna ◽

R. Kumar ◽

A. Basu

Keyword(s):

Architecture Design ◽

Instruction Set ◽

Switching Activity ◽

Instruction Set Architecture

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Formalizing GPU Instruction Set Architecture in Coq

Proceedings of the 12th Innovations on Software Engineering Conference (formerly known as India Software Engineering Conference) - ISEC'19 ◽

10.1145/3299771.3299798 ◽

2019 ◽

Author(s):

Nitin Bhatia ◽

Meenakshi D'Souza ◽

Sujit Kumar Chakrabarti

Keyword(s):

Instruction Set ◽

Instruction Set Architecture

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Vector Extensions, Instruction-Set Architecture (ISA)

Encyclopedia of Parallel Computing ◽

10.1007/978-0-387-09766-4_259 ◽

2011 ◽

pp. 2129-2135

Author(s):

Holger Brunst ◽

Andreas Knüpfer ◽

Valentina Salapura ◽

Joseph A. Fisher ◽

Paolo Faraboschi ◽

...

Keyword(s):

Instruction Set ◽

Instruction Set Architecture

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A complete formal semantics of x86-64 user-level instruction set architecture

Proceedings of the 40th ACM SIGPLAN Conference on Programming Language Design and Implementation - PLDI 2019 ◽

10.1145/3314221.3314601 ◽

2019 ◽

Author(s):

Sandeep Dasgupta ◽

Daejun Park ◽

Theodoros Kasampalis ◽

Vikram S. Adve ◽

Grigore Roşu

Keyword(s):

Formal Semantics ◽

Instruction Set ◽

Instruction Set Architecture

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An Isabelle/HOL Formalisation of the SPARC Instruction Set Architecture and the TSO Memory Model

Journal of Automated Reasoning ◽

10.1007/s10817-020-09579-4 ◽

2020 ◽

Author(s):

Zhé Hóu ◽

David Sanan ◽

Alwen Tiu ◽

Yang Liu ◽

Koh Chuen Hoa ◽

...

Keyword(s):

Memory Model ◽

Instruction Set ◽

Instruction Set Architecture

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