A Basic Microkernel for the RISC-V Instruction Set Architecture

ABSTRACTComputer processors provide an abstract model known as theinstruction set architecture, which serves as an interface betweenthe available hardware and the software. Application developersneed to communicate with these types of hardware, and having tolearn each computer specification is difficult and time-consuming.Operating systems provide an abstraction towards the availablecomputer hardware and user software. They manage computerresources to enable application programmers to communicate withthe available hardware. This work introduces an academic-orientedoperating system for the RISC-V architecture, a de facto instructionset architecture standard, and compares the solution with othersmall operating systems using the same architecture. As the maincontribution, this work provides an extensible operating system tointroduce students to operating system development.

Addressing Mode and Bit Extensions to the Thumb-2 Instruction Set Architecture

Thumb-2 is the most recent instruction set architecture for ARM processors which are one of the most widely used embedded processors. In this paper, two extensions are proposed to improve the performance of the Thumb-2 instruction set architecture, which are addressing mode extensions and sign/zero extensions combined with data processing instructions. To speed up access to an element of an aggregated data, the proposed approach first introduces three new addressing modes for load and store instructions. They are register-plus-immediate offset addressing mode, negative register offset addressing mode, and post-increment register offset addressing mode. Register-plus-immediate offset addressing mode permits two offsets and negative register offset allows offset to be a negative value of a register content. Post-increment register offset mode automatically modifies the offset address after the memory operation. The second is the sign/zero extension combined with a data processing instruction which allows the result of a data processing operation to be sign/zero extended to accelerate a type conversion. Several least frequently used instructions are reduced to provide the encoding space for the new extensions. Experiments show that the proposed approach improves performance by an average of 8.6% when compared to the Thumb-2 instruction set architecture.

A Review of ARM Processor Architecture History, Progress and Applications

Globally, over 50 billion ARM architecture based embedded chips of 32-bit and 64-bit instruction set architecture are commonly used and produced in quantity perspective since 2014. In our daily life most of the people uses and depends upon a penalty of electrical and automotive devices which have now become an essential part of their daily life. Due to that reason embedded processors are used to build such devices which takes less silicone-space, provides efficient processing and less power.