Coordinated parallelizing compiler optimizations and high-level synthesis

ACM Transactions on Design Automation of Electronic Systems ◽

10.1145/1027084.1027087 ◽

2004 ◽

Vol 9 (4) ◽

pp. 441-470 ◽

Author(s):

Sumit Gupta ◽

Rajesh Kumar Gupta ◽

Nikil D. Dutt ◽

Alexandru Nicolau

Keyword(s):

High Level Synthesis ◽

Parallelizing Compiler ◽

Compiler Optimizations ◽

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The Effect of Compiler Optimizations on High-Level Synthesis for FPGAs

2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines ◽

10.1109/fccm.2013.50 ◽

2013 ◽

Author(s):

Qijing Huang ◽

Ruolong Lian ◽

Andrew Canis ◽

Jongsok Choi ◽

Ryan Xi ◽

...

Keyword(s):

High Level Synthesis ◽

Compiler Optimizations ◽

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The Effect of Compiler Optimizations on High-Level Synthesis-Generated Hardware

ACM Transactions on Reconfigurable Technology and Systems ◽

10.1145/2629547 ◽

2015 ◽

Vol 8 (3) ◽

pp. 1-26 ◽

Author(s):

Qijing Huang ◽

Ruolong Lian ◽

Andrew Canis ◽

Jongsok Choi ◽

Ryan Xi ◽

...

Keyword(s):

High Level Synthesis ◽

Compiler Optimizations ◽

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Source-Level Compiler Optimizations for High-Level Synthesis

Proceedings of the SouthEast European Design Automation, Computer Engineering, Computer Networks and Social Media Conference on - SEEDA-CECNSM '16 ◽

10.1145/2984393.2984406 ◽

2016 ◽

Author(s):

Georgios Dimitriou ◽

Georgios Chatzianastasiou ◽

Apostolos Tsakyridis ◽

Georgios Stamoulis ◽

Michael Dossis

Keyword(s):

High Level Synthesis ◽

Compiler Optimizations ◽

Source Level ◽

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A Study on the Impact of Compiler Optimizations on High-Level Synthesis

Languages and Compilers for Parallel Computing - Lecture Notes in Computer Science ◽

10.1007/978-3-642-37658-0_10 ◽

2013 ◽

pp. 143-157 ◽

Author(s):

Jason Cong ◽

Bin Liu ◽

Raghu Prabhakar ◽

Peng Zhang

Keyword(s):

High Level Synthesis ◽

Compiler Optimizations ◽

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SPARK: a high-level synthesis framework for applying parallelizing compiler transformations

16th International Conference on VLSI Design, 2003. Proceedings. ◽

10.1109/icvd.2003.1183177 ◽

2003 ◽

Author(s):

S. Gupta ◽

N. Dutt ◽

R. Gupta ◽

A. Nicolau

Keyword(s):

High Level Synthesis ◽

Parallelizing Compiler ◽

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Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e92.a.3169 ◽

2009 ◽

Vol E92-A (12) ◽

pp. 3169-3179 ◽

Author(s):

Akira OHCHI ◽

Nozomu TOGAWA ◽

Masao YANAGISAWA ◽

Tatsuo OHTSUKI

Keyword(s):

High Level Synthesis ◽

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A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e100.a.1439 ◽

2017 ◽

Vol E100.A (7) ◽

pp. 1439-1451

Author(s):

Koki IGAWA ◽

Masao YANAGISAWA ◽

Nozomu TOGAWA

Keyword(s):

High Level Synthesis ◽

Synthesis Algorithm ◽

Body Biasing ◽

Delay Variation

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Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e97.a.2498 ◽

2014 ◽

Vol E97.A (12) ◽

pp. 2498-2506

Author(s):

Akihiro SUDA ◽

Hideki TAKASE ◽

Kazuyoshi TAKAGI ◽

Naofumi TAKAGI

Keyword(s):

High Level Synthesis ◽

Loop Parallelization ◽

Polyhedral Optimization ◽

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A parallel ant colony optimization to globally optimize area in high-level synthesis. (c2011)

10.26756/th.2011.36 ◽

2011 ◽

Author(s):

David Elias Kozhaya

Keyword(s):

Ant Colony Optimization ◽

High Level Synthesis ◽

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Language requirements for high-level synthesis

10.3403/00837025 ◽

1996 ◽

Keyword(s):

High Level Synthesis ◽

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