Estimation of lower bounds in scheduling algorithms for high-level synthesis

ACM Transactions on Design Automation of Electronic Systems ◽

10.1145/290833.290839 ◽

1998 ◽

Vol 3 (2) ◽

pp. 162-180 ◽

Author(s):

Giri Tiruvuri ◽

Moon Chung

Keyword(s):

Lower Bounds ◽

Scheduling Algorithms ◽

High Level Synthesis ◽

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A new technique for estimating lower bounds on latency for high level synthesis

Proceedings of the 10th Great Lakes Symposium on VLSI - GLSVLSI '00 ◽

10.1145/330855.331020 ◽

2000 ◽

Author(s):

Helvio P. Peixoto ◽

Margarida F. Jacome

Keyword(s):

Lower Bounds ◽

High Level Synthesis ◽

New Technique ◽

A New Technique ◽

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On lower bounds for scheduling problems in high-level synthesis

Proceedings 37th Design Automation Conference ◽

10.1145/337292.337573 ◽

2000 ◽

Author(s):

M. Narasimhan ◽

J. Ramanujam

Keyword(s):

Lower Bounds ◽

High Level Synthesis ◽

Scheduling Problems ◽

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Optimal and Heuristic Scheduling Algorithms for Asynchronous High-Level Synthesis

2011 17th IEEE International Symposium on Asynchronous Circuits and Systems ◽

10.1109/async.2011.18 ◽

2011 ◽

Author(s):

Nikos Andrikos ◽

Luciano Lavagno

Keyword(s):

Scheduling Algorithms ◽

High Level Synthesis ◽

Heuristic Scheduling ◽

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Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e92.a.3169 ◽

2009 ◽

Vol E92-A (12) ◽

pp. 3169-3179 ◽

Author(s):

Akira OHCHI ◽

Nozomu TOGAWA ◽

Masao YANAGISAWA ◽

Tatsuo OHTSUKI

Keyword(s):

High Level Synthesis ◽

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A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e100.a.1439 ◽

2017 ◽

Vol E100.A (7) ◽

pp. 1439-1451

Author(s):

Koki IGAWA ◽

Masao YANAGISAWA ◽

Nozomu TOGAWA

Keyword(s):

High Level Synthesis ◽

Synthesis Algorithm ◽

Body Biasing ◽

Delay Variation

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Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e97.a.2498 ◽

2014 ◽

Vol E97.A (12) ◽

pp. 2498-2506

Author(s):

Akihiro SUDA ◽

Hideki TAKASE ◽

Kazuyoshi TAKAGI ◽

Naofumi TAKAGI

Keyword(s):

High Level Synthesis ◽

Loop Parallelization ◽

Polyhedral Optimization ◽

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A parallel ant colony optimization to globally optimize area in high-level synthesis. (c2011)

10.26756/th.2011.36 ◽

2011 ◽

Author(s):

David Elias Kozhaya

Keyword(s):

Ant Colony Optimization ◽

High Level Synthesis ◽

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Language requirements for high-level synthesis

10.3403/00837025 ◽

1996 ◽

Keyword(s):

High Level Synthesis ◽

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Exact and Practical Modulo Scheduling for High-Level Synthesis

ACM Transactions on Reconfigurable Technology and Systems ◽

10.1145/3317670 ◽

2019 ◽

Vol 12 (2) ◽

pp. 1-26 ◽

Author(s):

Julian Oppermann ◽

Melanie Reuter-Oppermann ◽

Lukas Sommer ◽

Andreas Koch ◽

Oliver Sinnen

Keyword(s):

High Level Synthesis ◽

Modulo Scheduling ◽

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Implementation of Convolutional Neural Network with Co-design of High-Level Synthesis and Verilog HDL

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) ◽

10.1109/icsict49897.2020.9278149 ◽

2020 ◽

Author(s):

Hejie Yu ◽

Jun Cheng ◽

Xiangnan Zhang ◽

Yuzhe Gao ◽

Kuizhi Mei

Keyword(s):

Neural Network ◽

Convolutional Neural Network ◽

High Level Synthesis ◽

Verilog Hdl ◽

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