In this paper we provide a distributed solution to perform Design Rule Checking (DRC) of a layout by exploiting
either spatial independence or layer independence in layout data. We show that the former approach to DRC
can result in reasonable speedup only for large layouts, whereas, the latter approach shows a better performance
for smaller layouts. We also provide an algorithm to optimally partition a layout and a scheme to allocate DRC
tasks to idle processors in a Distributed Computing Environment (DCE) to attain load balancing.