Architecture Design of Network-on-Chip

2009 ◽

Cited By ~ 7

Author(s):

Yiou Chen ◽

Jianhao Hu ◽

Xiang Ling

Keyword(s):

Network On Chip ◽

De Bruijn Graph ◽

Architecture Design ◽

3D Network ◽

De Bruijn ◽

On Chip

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Architecture design principles for the integration of synchronization interfaces into Network-on-Chip switches

Proceedings of the 2nd International Workshop on Network on Chip Architectures - NoCArc '09 ◽

10.1145/1645213.1645222 ◽

2009 ◽

Cited By ~ 9

Author(s):

Daniele Ludovici ◽

Alessandro Strano ◽

Davide Bertozzi

Keyword(s):

Design Principles ◽

Network On Chip ◽

Architecture Design ◽

On Chip

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Efficient Router Architecture design on FPGA for Torus based Network on Chip

International Journal of Computer Applications ◽

10.5120/8824-2869 ◽

2012 ◽

Vol 55 (14) ◽

pp. 30-35

Author(s):

Saraswathi Venugopal ◽

Arokiasamy Arulanandasamy ◽

R. Ramachandran

Keyword(s):

Network On Chip ◽

Architecture Design ◽

Router Architecture ◽

On Chip

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PMCNOC: A Pipelining Multi-Channel Central Caching Network-on-Chip Communication Architecture Design

2007 IEEE Workshop on Signal Processing Systems ◽

10.1109/sips.2007.4387596 ◽

2007 ◽

Cited By ~ 3

Author(s):

Nan Wang ◽

Azeez Sanusi ◽

Peiyi Zhao ◽

Shaheen Mohamed ◽

Magdy A. Bayoumi

Keyword(s):

Network On Chip ◽

Architecture Design ◽

Communication Architecture ◽

On Chip

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Architecture Design of Network-on-Chip

Network-on-Chip ◽

10.1201/9781315216072-3 ◽

2018 ◽

pp. 53-74

Author(s):

Santanu Kundu ◽

Santanu Chattopadhyay

Keyword(s):

Network On Chip ◽

Architecture Design ◽

On Chip

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Network-on-chip architecture design based on mesh-of-tree deterministic routing topology

International Journal of High Performance Systems Architecture ◽

10.1504/ijhpsa.2008.021797 ◽

2008 ◽

Vol 1 (3) ◽

pp. 163 ◽

Cited By ~ 26

Author(s):

Santanu Kundu ◽

Santanu Chattopadhyay

Keyword(s):

Network On Chip ◽

Architecture Design ◽

Deterministic Routing ◽

On Chip

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Adaptive instruction codec architecture design for network-on-chip

Computers & Electrical Engineering ◽

10.1016/j.compeleceng.2016.02.021 ◽

2016 ◽

Vol 51 ◽

pp. 207-224

Author(s):

Trong-Yen Lee ◽

Chi-Han Huang ◽

Min-Jea Liu ◽

Jhen-Syuan Chen

Keyword(s):

Network On Chip ◽

Architecture Design ◽

Adaptive Instruction ◽

On Chip

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2-Level FIFO Architecture Design for Switch Fabrics in Network-on-Chip

2006 IEEE International Conference on Acoustics Speed and Signal Processing Proceedings ◽

10.1109/iscas.2006.1693720 ◽

2006 ◽

Cited By ~ 4

Author(s):

Po-Tsang Huang ◽

Wei Hwang

Keyword(s):

Network On Chip ◽

Architecture Design ◽

Switch Fabrics ◽

On Chip

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Micro-Architecture Design for Low Overhead Fault Tolerant Network-on-Chip

2018 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas.2018.8351501 ◽

2018 ◽

Cited By ~ 3

Author(s):

Chikun Yuan ◽

Letian Huang ◽

Junshi Wang ◽

Qiang Li

Keyword(s):

Fault Tolerant ◽

Network On Chip ◽

Architecture Design ◽

On Chip

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Service-Oriented Architecture Design for Virtualization in Network-on-Chip

2016 International Computer Symposium (ICS) ◽

10.1109/ics.2016.0030 ◽

2016 ◽

Author(s):

Chun-Hsian Huang ◽

Kwuan-Wei Tseng ◽

Pao-Ann Hsiung

Keyword(s):

Service Oriented Architecture ◽

Network On Chip ◽

Architecture Design ◽

Service Oriented ◽

On Chip

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Architecture Design of Network-on-Chip

De Bruijn graph based 3D Network on Chip architecture design

Architecture design principles for the integration of synchronization interfaces into Network-on-Chip switches

Efficient Router Architecture design on FPGA for Torus based Network on Chip

PMCNOC: A Pipelining Multi-Channel Central Caching Network-on-Chip Communication Architecture Design

Architecture Design of Network-on-Chip

Network-on-chip architecture design based on mesh-of-tree deterministic routing topology

Adaptive instruction codec architecture design for network-on-chip

2-Level FIFO Architecture Design for Switch Fabrics in Network-on-Chip

Micro-Architecture Design for Low Overhead Fault Tolerant Network-on-Chip

Service-Oriented Architecture Design for Virtualization in Network-on-Chip

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