Proceedings of the 2nd International Workshop on Network on Chip Architectures - NoCArc '09
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9781605587745

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The era of many-modules SoC

Proceedings of the 2nd International Workshop on Network on Chip Architectures - NoCArc '09 ◽

10.1145/1645213.1645224 ◽

2009 ◽

Author(s):

Isask'har Walter ◽

Israel Cidon ◽

Avinoam Kolodny ◽

Daniel Sigalov

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Breaking adaptive multicast deadlock by virtual channel address/data FIFO decoupling

Proceedings of the 2nd International Workshop on Network on Chip Architectures - NoCArc '09 ◽

10.1145/1645213.1645218 ◽

2009 ◽

Author(s):

Ka-Ming Keung ◽

Akhilesh Tyagi

Keyword(s):

Virtual Channel ◽

Address Data ◽

Adaptive Multicast

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Architecture design principles for the integration of synchronization interfaces into Network-on-Chip switches

Proceedings of the 2nd International Workshop on Network on Chip Architectures - NoCArc '09 ◽

10.1145/1645213.1645222 ◽

2009 ◽

Author(s):

Daniele Ludovici ◽

Alessandro Strano ◽

Davide Bertozzi

Keyword(s):

Design Principles ◽

Network On Chip ◽

Architecture Design ◽

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Router microarchitecture and scalability of ring topology in on-chip networks

Proceedings of the 2nd International Workshop on Network on Chip Architectures - NoCArc '09 ◽

10.1145/1645213.1645217 ◽

2009 ◽

Author(s):

John Kim ◽

Hanjoon Kim

Keyword(s):

Ring Topology ◽

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Hybrid wireless Network on Chip

Proceedings of the 2nd International Workshop on Network on Chip Architectures - NoCArc '09 ◽

10.1145/1645213.1645230 ◽

2009 ◽

Author(s):

Partha Pratim Pande ◽

Amlan Ganguly ◽

Kevin Chang ◽

Christof Teuscher

Keyword(s):

Wireless Network ◽

Network On Chip ◽

Hybrid Wireless Network ◽

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Yield enhancement by robust application-specific mapping on Network-on-Chips

Proceedings of the 2nd International Workshop on Network on Chip Architectures - NoCArc '09 ◽

10.1145/1645213.1645223 ◽

2009 ◽

Author(s):

A. Dutta Choudhury ◽

G. Palermo ◽

C. Silvano ◽

V. Zaccaria

Keyword(s):

Yield Enhancement ◽

Specific Mapping ◽

Application Specific

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A performance evaluation of 2D-mesh, ring, and crossbar interconnects for chip multi-processors

Proceedings of the 2nd International Workshop on Network on Chip Architectures - NoCArc '09 ◽

10.1145/1645213.1645226 ◽

2009 ◽

Author(s):

Jesús Camacho Villanueva ◽

José Flich ◽

José Duato ◽

Hans Eberle ◽

Nils Gura ◽

...

Keyword(s):

Performance Evaluation ◽

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Toward a science for future NoC design

Proceedings of the 2nd International Workshop on Network on Chip Architectures - NoCArc '09 ◽

10.1145/1645213.1645215 ◽

2009 ◽

Author(s):

Radu Marculescu

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Scalable arbitration of partitioned bus interconnection networks in 3D-IC systems

Proceedings of the 2nd International Workshop on Network on Chip Architectures - NoCArc '09 ◽

10.1145/1645213.1645231 ◽

2009 ◽

Author(s):

Kelli Ireland ◽

Joseph Jezak ◽

Steven Levitan ◽

Donald Chiarulli

Keyword(s):

Interconnection Networks ◽

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Segment gating for static energy reduction in Networks-on-Chip

Proceedings of the 2nd International Workshop on Network on Chip Architectures - NoCArc '09 ◽

10.1145/1645213.1645227 ◽

2009 ◽

Author(s):

Kyle C. Hale ◽

Boris Grot ◽

Stephen W. Keckler

Keyword(s):

Energy Reduction ◽

Networks On Chip ◽

Static Energy ◽

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