Savior: A Reliable Fault Resilient Router Architecture for Network-on-Chip

The router plays an important role in communication among different processing cores in on-chip networks. Technology scaling on one hand has enabled the designers to integrate multiple processing components on a single chip; on the other hand, it becomes the reason for faults. A generic router consists of the buffers and pipeline stages. A single fault may result in an undesirable situation of degraded performance or a whole chip may stop working. Therefore, it is necessary to provide permanent fault tolerance to all the components of the router. In this paper, we propose a mechanism that can tolerate permanent faults that occur in the router. We exploit the fault-tolerant techniques of resource sharing and paring between components for the input port unit and routing computation (RC) unit, the resource borrowing for virtual channel allocator (VA) and multiple paths for switch allocator (SA) and crossbar (XB). The experimental results and analysis show that the proposed mechanism enhances the reliability of the router architecture towards permanent faults at the cost of 29% area overhead. The proposed router architecture achieves the highest Silicon Protection Factor (SPF) metric, which is 24.8 as compared to the state-of-the-art fault-tolerant architectures. It incurs an increase in latency for SPLASH2 and PARSEC benchmark traffics, which is minimal as compared to the baseline router.

Protector: A Permanent Fault Resilient Router Architecture for Network on Chip

The decreasing size of the transistor has increased the vulnerability towards faults. Increasing number of cores on a single chip has made the concept of Network on Chip (NoC) a standard communication backbone among cores. This facility comes with vulnerability of faults in the system due to decreasing size of transistors. A permanent fault in the network leads to undesirable consequence such as permanent blocking of flits or failure of the whole router. Preserving the router in the operational state has a significant impact on the reliability of the system. Permanent fault in buffers and pipeline stages of the router has a high impact on performance. The proposed router architecture Protector provides faults protection to both buffers and pipelines stages by exploiting the concepts of borrowing from other resources, using bypass paths and by creating multiple paths to reach output. The proposed router incurred an area overhead of 30% as compared to the baseline design. Reliability analysis using Silicon Protection Factor indicates that the proposed router has better fault tolerance efficiency as compared to state of the art. Latency analysis using PARSEC and SPLASH-2 benchmarks indicates proposed router incurs 13% and 16% latency overhead in the presence of faults.

An Efficient 4X4 Mesh Structure with a Combination of Two NoC Router Architecture

: Network-on-Chip is used to integrate large numbers of Intellectual Property blocks on a single Integrated Chip. NoC router is one of the important parts of networking that is used inside a Chip. There are various topologies used in NoC network, mesh topology is one of them. In a conventional mesh structure, a defined NoC router is implemented at every node of the mesh structure. In this paper, a new 4x4 mesh structure is proposed and analyzed in which a combination of two different NoC router is implemented in a single mesh structure. Proposed mesh structure consists of one conventional NoC router and a new proposed NoC router which is designed in such a way that it can only transfer its input channel data into two output channel. To achieve this two-directional data transfer requirement, component of NoC router such as Crossbar switch, buffers are changed. This new proposed NoC router Architecture model is simulated in Xilinx ISE 9.2i and its targeted device is Virtex4. Where its area, power, is calculated. Then based on this result, an analysis for area and power is performed for Proposed 4x4 mesh structure. And this result analysis shows 17.24 % reduction in the area of proposed 4X4 mesh structure as compared to conventional 4X4 Mesh architecture. Further, this analysis also performed for 8x8, 16x16, 32x32 mesh structures. As the number of processors inside an SoC (System on a Chip) of a Mobile is increasing, the bus-based system can be replaced by an NoC system for better performance. The presented paper describes the effective utilization of NoC capabilities for next-generation mobile phones.

NoCGuard: A Reliable Network-on-Chip Router Architecture

Aggressive scaling in deep nanometer technology enables chip multiprocessor design facilitated by the communication-centric architecture provided by Network-on-Chip (NoC). At the same time, it brings considerable challenges in reliability because a fault in the network architecture severely impacts the performance of a system. To deal with these reliability challenges, this research proposed NoCGuard, a reconfigurable architecture designed to tolerate multiple permanent faults in each pipeline stage of the generic router. NoCGuard router architecture uses four highly reliable and low-cost fault-tolerant strategies. We exploited resource borrowing and double routing strategy for the routing computation stage, default winner strategy for the virtual channel allocation stage, runtime arbiter selection and default winner strategy for the switch allocation stage and multiple secondary bypass paths strategy for the crossbar stage. Unlike existing reliable router architectures, our architecture features less redundancy, more fault tolerance, and high reliability. Reliability comparison using Mean Time to Failure (MTTF) metric shows 5.53-time improvement in a lifetime and using Silicon Protection Factor (SPF), 22-time improvement, which is better than state-of-the-art reliable router architectures. Synthesis results using 15 nm and 45 nm technology library show that additional circuitry incurs an area overhead of 28.7% and 28% respectively. Latency analysis using synthetic, PARSEC and SPLASH-2 traffic shows minor increase in performance by 3.41%, 12% and 15% respectively while providing high reliability.