scholarly journals Implementation of reconfigurable galois field multipliers over2m using primitive polynomials

2018 ◽  
Vol 7 (2.12) ◽  
pp. 386
Author(s):  
B Raj Narain ◽  
Dr T. Sasilatha
Keyword(s):  
Galois Field ◽  
Hardware Architecture ◽  
Fixed Length ◽  
Primitive Polynomials

The Galois field multiplier finds extensive use in cryptographic solutions and applications. The Galois field multiplier can be implemented as fixed bitwise or reconfigurable. For fixed length, the data is restricted to the fixed length. But in reconfigurable GF multipliers, the bit length of the multiplier is flexible and is independent of hardware architecture. This paper proposes a method to implement a reconfigurable GF multiplier for various bit values from 8 to 128 bits. This paper compares the area complexity of various bit size in Xilinx Spartan 3E family FPGA and estimates the resources required for the implementation.  

scholarly journals Construction and Determination of Irreducible Polynomials in Galois elds, GF(2m)

2019 ◽  
pp. 1-6
Author(s):  
Abraham Aidoo ◽  
Kwasi Baah Gyam ◽  
Fengfan Yang
Keyword(s):  
Finite Field ◽  
Finite Fields ◽  
Monic Polynomial ◽  
Galois Field ◽  
Irreducible Polynomials ◽  
Primitive Polynomials

This work is about Construction of Irreducible Polynomials in Finite fields. We defined some terms in the Galois field that led us to the construction of the polynomials in the GF(2m). We discussed the following in the text; irreducible polynomials, monic polynomial, primitive polynomials, eld, Galois eld or nite elds, and the order of a finite field. We found all the polynomials in $$F_2[x]$$ that is, $$P(x) =\sum_{i=1}^m a_ix^i : a_i \in F_2$$ with $$a_m \neq 0$$ for some degree $m$ whichled us to determine the number of irreducible polynomials generally at any degree in $$F_2[x]$$.

scholarly journals Construction of Irreducible Polynomials in Galois elds, GF(2m) Using Normal Bases

2019 ◽  
pp. 1-15
Author(s):  
Abraham Aidoo ◽  
Kwasi Baah Gyam
Keyword(s):  
Finite Field ◽  
Finite Fields ◽  
General Rule ◽  
Galois Field ◽  
Irreducible Polynomials ◽  
Galois Fields ◽  
Normal Bases ◽  
Primitive Polynomials

This thesis is about Construction of Polynomials in Galois fields Using Normal Bases in finite fields. In this piece of work, we discussed the following in the text; irreducible polynomials, primitive polynomials, field, Galois field or finite fields, and the order of a finite field. We found the actual construction of polynomials in GF(2m) with degree less than or equal to m − 1 and also illustrated how this construction can be done using normal bases. Finally, we found the general rule for construction of GF(pm) using normal bases and even the rule for producing reducible polynomials.

A Fixed Field/Fixed Length Automated Case Record Using an IBM 1232 Optically Readable Document

1968 ◽  
Vol 07 (03) ◽  
pp. 156-158
Author(s):  
Th. R. Taylor
Keyword(s):  
Clinical Data ◽  
Case Record ◽  
Fixed Field ◽  
Fixed Length

The technique, scope and limitations of a fixed field/fixed length case record utilising the IBM 1232 system is described. The principal problems lie with personnel rather than machinery and with programmes for analysis rather than clinical data.

A New Hardware Architecture for Fuzzy Logic System Acceleration

2016 ◽  
Vol 12 (2) ◽  
pp. 188-197
Author(s):  
A yahoo.com ◽  
Aumalhuda Gani Abood aumalhuda ◽  
A comp ◽  
Dr. Mohammed A. Jodha ◽  
Dr. Majid A. Alwan
Keyword(s):  
Fuzzy Logic ◽  
Fuzzy Logic System ◽  
Hardware Architecture ◽  
Logic System

4D-DCT Hardware Architecture for JPEG Pleno Light Field Coding

2020 ◽  
Author(s):  
Matheus Jahnke ◽  
Jones Goebel ◽  
Daniel Palomino ◽  
Guilherme Correa ◽  
Luciano Agostini ◽  
...  
Keyword(s):  
Light Field ◽  
Hardware Architecture

scholarly journals Real-time FPGA-based implementation of the AKAZE algorithm with nonlinear scale space generation using image partitioning

2021 ◽  
Author(s):  
Parastoo Soleimani ◽  
David W. Capson ◽  
Kin Fun Li
Keyword(s):  
Real Time ◽  
Memory Management ◽  
Scale Space ◽  
Image Resolution ◽  
Hardware Architecture ◽  
Frame Rate ◽  
Time Sharing ◽  
Scale Invariant ◽  
Nonlinear Scale Space ◽  
Nonlinear Scale

AbstractThe first step in a scale invariant image matching system is scale space generation. Nonlinear scale space generation algorithms such as AKAZE, reduce noise and distortion in different scales while retaining the borders and key-points of the image. An FPGA-based hardware architecture for AKAZE nonlinear scale space generation is proposed to speed up this algorithm for real-time applications. The three contributions of this work are (1) mapping the two passes of the AKAZE algorithm onto a hardware architecture that realizes parallel processing of multiple sections, (2) multi-scale line buffers which can be used for different scales, and (3) a time-sharing mechanism in the memory management unit to process multiple sections of the image in parallel. We propose a time-sharing mechanism for memory management to prevent artifacts as a result of separating the process of image partitioning. We also use approximations in the algorithm to make hardware implementation more efficient while maintaining the repeatability of the detection. A frame rate of 304 frames per second for a $$1280 \times 768$$ 1280 × 768 image resolution is achieved which is favorably faster in comparison with other work.

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