When Massive GPU Parallelism Ain’t Enough: A Novel Hardware Architecture of 2D-LSTM Neural Network

Multidimensional Long Short-Term Memory (MD-LSTM) neural network is an extension of one-dimensional LSTM for data with more than one dimension. MD-LSTM achieves state-of-the-art results in various applications, including handwritten text recognition, medical imaging, and many more. However, its implementation suffers from the inherently sequential execution that tremendously slows down both training and inference compared to other neural networks. The main goal of the current research is to provide acceleration for inference of MD-LSTM. We advocate that Field-Programmable Gate Array (FPGA) is an alternative platform for deep learning that can offer a solution when the massive parallelism of GPUs does not provide the necessary performance required by the application. In this article, we present the first hardware architecture for MD-LSTM. We conduct a systematic exploration to analyze a tradeoff between precision and accuracy. We use a challenging dataset for semantic segmentation, namely historical document image binarization from the DIBCO 2017 contest and a well-known MNIST dataset for handwritten digit recognition. Based on our new architecture, we implement FPGA-based accelerators that outperform Nvidia Geforce RTX 2080 Ti with respect to throughput by up to 9.9 and Nvidia Jetson AGX Xavier with respect to energy efficiency by up to 48 . Our accelerators achieve higher throughput, energy efficiency, and resource efficiency than FPGA-based implementations of convolutional neural networks (CNNs) for semantic segmentation tasks. For the handwritten digit recognition task, our FPGA implementations provide higher accuracy and can be considered as a solution when accuracy is a priority. Furthermore, they outperform earlier FPGA implementations of one-dimensional LSTMs with respect to throughput, energy efficiency, and resource efficiency.

Hardware Architecture for Asynchronous Cellular Self-Organizing Maps

Nowadays, one of the main challenges in computer architectures is scalability; indeed, novel processor architectures can include thousands of processing elements on a single chip and using them efficiently remains a big issue. An interesting source of inspiration for handling scalability is the mammalian brain and different works on neuromorphic computation have attempted to address this question. The Self-configurable 3D Cellular Adaptive Platform (SCALP) has been designed with the goal of prototyping such types of systems and has led to the proposal of the Cellular Self-Organizing Maps (CSOM) algorithm. In this paper, we present a hardware architecture for CSOM in the form of interconnected neural units with the specific property of supporting an asynchronous deployment on a multi-FPGA 3D array. The Asynchronous CSOM (ACSOM) algorithm exploits the underlying Network-on-Chip structure to be provided by SCALP in order to overcome the multi-path propagation issue presented by a straightforward CSOM implementation. We explore its behaviour under different map topologies and scalar representations. The results suggest that a larger network size with low precision coding obtains an optimal ratio between algorithm accuracy and FPGA resources.

Virtual Power Plant Platform for Demand Response Based on Microservice Architecture

It is a trend to use virtual power plant technology to realize demand response and participate in electricity trading. We design and implement the software control platform of virtual power plant for demand response. For this software platform, we analysed the requirements and got the overall architecture of the platform. On this basis, we design and implement the microservice architecture, interface design, basic application function design, advanced application function design, hardware architecture, communication architecture and security encryption of the platform. Finally, we summarize the application of the platform, and put forward the direction of further research and development.

FPGA Implementation of Eye Movement Detection Algorithm

In this paper, we propose an simple and efficient VLSI hardware architecture is implemented for eye movement detection. For Eye movement detection reading activity Electrooculography (EOG) signal is considered. Here, for denoising the noisy EOG signal efficient FIR filter and for decomposition of denoised EOG signal an efficient Haar wavelet transform architecture is used respectively. The modified VLSI hardware architecture method detected the saccade (left movement of eye and right movement of eye) and blink efficiently. The hardware architecture of the eye movement detection algorithm functionality is verified by using Xilinx System Generator hardware co-simulation tool. The eye movement detection algorithm is implemented on the ZedBoard FPGA using Xilinx Vivado design suite.

FPGA REALIZATION OF COMPLEX LOGISTIC MAP FRACTAL BEHAVIOR

This paper studies the capability of digital architecture to mimic fractal behavior. As chaotic attractors realized digitally had opened many tracks, digital designs mimicking fractals may ultimately achieve the same. This study is based on a complex single-dimensional discrete chaotic system known as the generalized positive logistic map. The fractals realized from this system are linked to the results of the mathematical analysis to understand the fractal behavior with different variations. A digital hardware architecture manifesting the fractal behavior is achieved on FPGA, showing a fractal entity experimentally. With this digital realization, it is hoped that fractals can follow the example of chaotic attractors digital applications.

Design and analysis of Maxwell fisheye lens based beamformer

Antenna arrays and multi-antenna systems are essential in beyond 5G wireless networks for providing wireless connectivity, especially in the context of Internet-of-Everything. To facilitate this requirement, beamforming technology is emerging as a key enabling solution for adaptive on-demand wireless coverage. Despite digital beamforming being the primary choice for adaptive wireless coverage, a set of applications rely on pure analogue beamforming approaches, e.g., in point-to-multi point and physical-layer secure communication links. In this work, we present a novel scalable analogue beamforming hardware architecture that is capable of adaptive 2.5-dimensional beam steering and beam shaping to fulfil the coverage requirements. Beamformer hardware comprises of a finite size Maxwell fisheye lens used as a scalable feed network solution for a semi-circular array of monopole antennas. This unique hardware architecture enables a flexibility of using 2 to 8 antenna elements. Beamformer development stages are presented while experimental beam steering and beam shaping results show good agreement with the estimated performance.