Real Time Network on Chip (NOC) Architecture with CDMA Techniques with Audio Decoders

2018 ◽  
Keyword(s):  
Real Time ◽  
Network On Chip ◽  
On Chip

Failure analysis of a network-on-chip for real-time mixed-critical systems

2014 ◽  
Author(s):  
Eberle A. Rambo ◽  
Alexander Tschiene ◽  
Jonas Diemer ◽  
Leonie Ahrendts ◽  
Rolf Ernst
Keyword(s):  
Failure Analysis ◽  
Real Time ◽  
Network On Chip ◽  
Critical Systems ◽  
On Chip

Failure analysis of a network-on-chip for real-time mixed-critical systems

2014 ◽  
Author(s):  
Eberle A. Rambo ◽  
Alexander Tschiene ◽  
Jonas Diemer ◽  
Leonie Ahrendts ◽  
Rolf Ernst
Keyword(s):  
Failure Analysis ◽  
Real Time ◽  
Network On Chip ◽  
Critical Systems ◽  
On Chip

Self-Aware Network-on-Chip Control in Real-Time Systems

2018 ◽  
Vol 35 (5) ◽  
pp. 19-27 ◽  
Author(s):  
Adam Kostrzewa ◽  
Sebastian Tobuschat ◽  
Rolf Ernst
Keyword(s):  
Real Time ◽  
Network On Chip ◽  
Real Time Systems ◽  
On Chip ◽  
Time Systems

Action-Level Real-Time Network-on-Chip Modeling

2017 ◽  
Vol 77 ◽  
pp. 272-291 ◽  
Author(s):  
Soroosh Gholami ◽  
Hessam S. Sarjoughian
Keyword(s):  
Real Time ◽  
Network On Chip ◽  
On Chip

scholarly journals Network-on-Chip Irregular Topology Optimization for Real-Time and Non-Real-Time Applications

Micromachines ◽  
2021 ◽  
Vol 12 (10) ◽  
pp. 1196
Author(s):  
Samuel da Silva Oliveira ◽  
Bruno Motta de Carvalho ◽  
Márcio Eduardo Kreutz
Keyword(s):  
Real Time ◽  
Communication Networks ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Network On Chip ◽  
Chip Area ◽  
Average Latency ◽  
Real Time Applications ◽  
On Chip

Network-on-Chip is a good approach to working on intra-chip communication. Networks with irregular topologies may be better suited for specific applications because of their architectural nature. A good design space exploration can help the design of the network to obtain more optimized topologies. This paper proposes a way of optimizing networks with irregular topologies through the use of a genetic algorithm. The network proposed here has heterogeneous routers that aim to optimize the network and support applications with real-time tasks. The goal is to find networks that are optimized for average latency and percentage of real-time packets delivered within the deadline. The results show that we have been able to find networks that can deliver all the real-time packets, obtain acceptable latency values, and shrink the chip area.

scholarly journals Virtual Channel aware Scheduling for Real Time Data-Flows on Network on-Chip

2019 ◽  
Vol 20 (3) ◽  
pp. 495-510
Author(s):  
Amine Meghabber ◽  
Lakhdar Loukil ◽  
Richard Olejnik ◽  
Abou El Hassan Benyamina ◽  
Abdelkader Aroui
Keyword(s):  
Real Time ◽  
Network On Chip ◽  
Time Constraints ◽  
Time Data ◽  
Virtual Channels ◽  
Software Designers ◽  
Data Flows ◽  
Real Time Data ◽  
Real Time Applications ◽  
On Chip

The increasing complexity of real-time applications presents a challenge to researchers and software designers. The tasks of these applications usually exchange large volume of data-flows and often need to satisfy real-time constraints. Although the Network on-Chip (NoC) paradigm offers an underlying communication infrastructure that gives more hardware resources, it is unable to safe tasks and data-flows deadlines. In recent works, preemptive wormhole switching with fixed priority has been introduced to meet real-time constraints of real-time applications. However, it suffers some bottleneck such as hardware requirement where none of these works takes account of the number of implemented virtual channels on the router. To alleviate this problem, we propose a novel scheduler for soft real-time data-flows application that takes into account the lack on resource in routers in term of Virtual channels. Experimental results obtained on a benchmark of synthetic and soft real applications have shown the efficiency of our approach in term of real-time constraints satisfaction for data-flow traffics and hardware requirements.

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