Matrix multiplier architecture for QC-LDPC code with minimum FPGA block RAM resource using
Keyword(s):
2009 ◽
Vol E92-B
(5)
◽
pp. 1504-1515
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2021 ◽
Vol 1873
(1)
◽
pp. 012018
Keyword(s):
2012 ◽
Vol 59
(6)
◽
pp. 381-385
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