Matrix multiplier architecture for QC-LDPC code with minimum FPGA block RAM resource using

Author(s):  
Denis V. Shekhalev ◽  
Keyword(s):  
2009 ◽  
Vol E92-B (5) ◽  
pp. 1504-1515 ◽  
Author(s):  
Naoto OKUBO ◽  
Nobuhiko MIKI ◽  
Yoshihisa KISHIYAMA ◽  
Kenichi HIGUCHI ◽  
Mamoru SAWAHASHI

Sign in / Sign up

Export Citation Format

Share Document