Reduced-Complexity LDPC Decoding for Next-Generation IoT Networks

Low-density parity-check (LDPC) codes have become the focal choice for next-generation Internet of things (IoT) networks. This correspondence proposes an efficient decoding algorithm, dual min-sum (DMS), to estimate the first two minima from a set of variable nodes for check-node update (CNU) operation of min-sum (MS) LDPC decoder. The proposed architecture entirely eliminates the large-sized multiplexing system of sorting-based architecture which results in a prominent decrement in hardware complexity and critical delay. Specifically, the DMS architecture eliminates a large number of comparators and multiplexors while keeping the critical delay equal to the most delay-efficient tree-based architecture. Based on experimental results, if the number of inputs is equal to 64, the proposed architecture saves 69%, 68%, and 52% area over the sorting-based, the tree-based, and the low-complexity tree-based architectures, respectively. Furthermore, the simulation results show that the proposed approach provides an excellent error-correction performance in terms of bit error rate (BER) and block error rate (BLER) over an additive white Gaussian noise (AWGN) channel.

ONE-MINIUM-ONLY BASIC-SET TRELLIS MIN-MAX DECODER ARCHITECTURE FOR NONBINARY LDPC CODE

Nonbinary low-density-parity-check (NB-LDPC) code outperforms their binary counterpart in terms of error-correcting performance and error-floor property when the code length is moderate. However, the drawback of NB-LDPC decoders is high complexity and the complexity increases considerably when increasing the Galois-field order. In this paper, an One-Minimum-Only basic-set trellis min-max (OMO-BS-TMM) algorithm and the corresponding decoder architecture are proposed for NBLDPC codes to greatly reduce the complexity of the check node unit (CNU) as well as the whole decoder. In the proposed OMO-BS-TMM algorithm, only the first minimum values are used for generating the check node messages instead of using both the first and second minimum values, and the number of messages exchanged between the check node and the variable node is reduced in comparison with the previous works. Layered decoder architectures based on the proposed algorithm were implemented for the (837, 726) NB-LDPC code over GF(32) using 90-nm CMOS technology. The implementation results showed that the OMO-BS-TMM algorithm achieves the almost similar error-correcting performance, and a reduction of the complexity by 31.8% and 20.5% for the whole decoder, compared to previous works. Moreover, the proposed decoder achieves a higher throughput at 1.4 Gbps, compared with the other state-of-the-art NBLDPC decoders.

Low-Complexity High-Throughput QC-LDPC Decoder for 5G New Radio Wireless Communication

This paper presents a pipelined layered quasi-cyclic low-density parity-check (QC-LDPC) decoder architecture targeting low-complexity, high-throughput, and efficient use of hardware resources compliant with the specifications of 5G new radio (NR) wireless communication standard. First, a combined min-sum (CMS) decoding algorithm, which is a combination of the offset min-sum and the original min-sum algorithm, is proposed. Then, a low-complexity and high-throughput pipelined layered QC-LDPC decoder architecture for enhanced mobile broadband specifications in 5G NR wireless standards based on CMS algorithm with pipeline layered scheduling is presented. Enhanced versions of check node-based processor architectures are proposed to improve the complexity of the LDPC decoders. An efficient minimum-finder for the check node unit architecture that reduces the hardware required for the computation of the first two minima is introduced. Moreover, a low complexity a posteriori information update unit architecture, which only requires one adder array for their operations, is presented. The proposed architecture shows significant improvements in terms of area and throughput compared to other QC-LDPC decoder architectures available in the literature.

A joint design method of frame synchronization code and LDPC code

Frame synchronization word (FSW) is an important basis in signal synchronization detection. In our work, the joint design of frame synchronization words and error correcting code are proposed which through regularly distributing the frame synchronization words among the information bits to improve the decoding performance of the LDPC. Frame synchronization word should be added to the information sequence corresponding to the position with the check matrix larger column weight which can guarantee that more Frame synchronization words are received by the check node in the decoding iteration. The frame synchronization word is known to the receiver which play an important role in decoding iteration. The results of simulation show that the algorithm makes an obvious improvement in decoding performance when the signal-noise ratio (SNR) is lower than 1 dB.

Graph-Based Detection and LDPC Decoding over 2D Intersymbol Interference Channels

In this paper, we propose a fully graph-based iterative detection and decoding scheme for Low-Density Parity-Check (LDPC) coded generalized two-dimensional (2D) intersymbol interference (ISI) channels. The 2D detector consists of a downtrack detector based on the symbol-level sum-product algorithm (SPA) and a bit-level SPA-based crosstrack detector. A LDPC decoder based on simplified check node operations is also proposed to provide soft information for the 2D channel detector. Numerical results show that the proposed receiver achieves better performance as compared with the trellis-based BCJR detector over 2×2 2D channels while at a significantly lower computational complexity.