wire planning Latest Research Papers

2017 ◽

Vol 25 (2) ◽

pp. 581-593 ◽

Cited By ~ 1

Author(s):

Shao-Yun Fang ◽

Kuo-Hao Wu

Keyword(s):

Wire Planning

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Novel Wire Planning Schemes for Pin Minimization in Digital Microfluidic Biochips

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2016.2541671 ◽

2016 ◽

Vol 24 (11) ◽

pp. 3345-3358 ◽

Cited By ~ 3

Author(s):

Pranab Roy ◽

Swati Saha ◽

Hafizur Rahaman ◽

Parthasarathi Dasgupta

Keyword(s):

Microfluidic Biochips ◽

Digital Microfluidic ◽

Wire Planning

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Cut mask optimization with wire planning in self-aligned multiple patterning full-chip routing

The 20th Asia and South Pacific Design Automation Conference ◽

10.1109/aspdac.2015.7059037 ◽

2015 ◽

Cited By ~ 10

Author(s):

Shao-Yun Fang

Keyword(s):

Wire Planning

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A Novel Wire Planning Technique for Optimum Pin Utilization in Digital Microfluidic Biochips

2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems ◽

10.1109/vlsid.2014.95 ◽

2014 ◽

Cited By ~ 2

Author(s):

Pranab Roy ◽

Samadrita Bhattacharya ◽

Rupam Bhattacharyay ◽

Firdousi Jamil Imam ◽

Hafizur Rahaman ◽

...

Keyword(s):

Microfluidic Biochips ◽

Planning Technique ◽

Digital Microfluidic ◽

Wire Planning

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Board- and Chip-Aware Package Wire Planning

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2012.2212288 ◽

2013 ◽

Vol 21 (8) ◽

pp. 1377-1387 ◽

Cited By ~ 1

Author(s):

Ren-Jie Lee ◽

Hsin-Wu Hsu ◽

Hung-Ming Chen

Keyword(s):

Wire Planning

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Wire Planning for Electromigration and Interference Avoidance in Analog Circuits

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e94.a.2402 ◽

2011 ◽

Vol E94-A (11) ◽

pp. 2402-2411

Author(s):

Hsin-Hsiung HUANG ◽

Jui-Hung HUNG ◽

Cheng-Chiang LIN ◽

Tsai-Ming HSIEH

Keyword(s):

Analog Circuits ◽

Interference Avoidance ◽

Wire Planning

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TROY: Track Router with Yield-driven Wire Planning

2007 44th ACM/IEEE Design Automation Conference ◽

10.1109/dac.2007.375124 ◽

2007 ◽

Cited By ~ 2

Author(s):

Minsik Cho ◽

Hua Xiang ◽

Ruchir Puri ◽

David Z. Pan

Keyword(s):

Wire Planning

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Wire Planning with Bounded Over-the-Block Wires

Sixth International Symposium on Quality of Electronic Design (ISQED'05) ◽

10.1109/isqed.2005.130 ◽

2005 ◽

Cited By ~ 1

Author(s):

Hua Xiang ◽

I-Min Liu ◽

M.D.F. Wong

Keyword(s):

Wire Planning

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A global wire planning scheme for Network-on-Chip

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03. ◽

10.1109/iscas.2003.1206364 ◽

2003 ◽

Cited By ~ 4

Author(s):

J. Liu ◽

L.-R. Zheng ◽

D. Pamunuwa ◽

H. Tenhunen

Keyword(s):

Network On Chip ◽

Planning Scheme ◽

On Chip ◽

Wire Planning

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Current-driven wire planning for electromigration avoidance in analog circuits

Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003. ◽

10.1109/aspdac.2003.1195125 ◽

2003 ◽

Cited By ~ 12

Author(s):

J. Lienig ◽

G. Jerke

Keyword(s):

Analog Circuits ◽

Wire Planning

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wire planning
Recently Published Documents

TOTAL DOCUMENTS

H-INDEX

Cut Mask Optimization With Wire Planning in Self-Aligned Multiple Patterning Full-Chip Routing

Novel Wire Planning Schemes for Pin Minimization in Digital Microfluidic Biochips

Cut mask optimization with wire planning in self-aligned multiple patterning full-chip routing

A Novel Wire Planning Technique for Optimum Pin Utilization in Digital Microfluidic Biochips

Board- and Chip-Aware Package Wire Planning

Wire Planning for Electromigration and Interference Avoidance in Analog Circuits

TROY: Track Router with Yield-driven Wire Planning

Wire Planning with Bounded Over-the-Block Wires

A global wire planning scheme for Network-on-Chip

Current-driven wire planning for electromigration avoidance in analog circuits

Export Citation Format

wire planningRecently Published Documents

TOTAL DOCUMENTS

H-INDEX

Cut Mask Optimization With Wire Planning in Self-Aligned Multiple Patterning Full-Chip Routing

Novel Wire Planning Schemes for Pin Minimization in Digital Microfluidic Biochips

Cut mask optimization with wire planning in self-aligned multiple patterning full-chip routing

A Novel Wire Planning Technique for Optimum Pin Utilization in Digital Microfluidic Biochips

Board- and Chip-Aware Package Wire Planning

Wire Planning for Electromigration and Interference Avoidance in Analog Circuits

TROY: Track Router with Yield-driven Wire Planning

Wire Planning with Bounded Over-the-Block Wires

A global wire planning scheme for Network-on-Chip

Current-driven wire planning for electromigration avoidance in analog circuits

wire planning
Recently Published Documents