[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers
Latest Publications

TOTAL DOCUMENTS

121

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE Comput. Soc. Press

0818608692

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

CHAMP: concurrent hierarchical and multilevel program for simulation of VLSI circuits

[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers ◽

10.1109/iccad.1988.122503 ◽

2003 ◽

Cited By ~ 19

Author(s):

D.G. Saab ◽

R.B. Mueller-Thuns ◽

D. Blaauw ◽

J.A. Abraham ◽

J.T. Rahmeh

Keyword(s):

Vlsi Circuits

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Compaction of ATPG-generated test sequences for sequential circuits

[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers ◽

10.1109/iccad.1988.122533 ◽

2003 ◽

Cited By ~ 35

Author(s):

R.K. Roy ◽

T.M. Niermann ◽

J.H. Patel ◽

J.A. Abraham ◽

R.A. Saleh

Keyword(s):

Sequential Circuits

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Discrete-event simulation on hypercube architectures

[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers ◽

10.1109/iccad.1988.122509 ◽

2003 ◽

Cited By ~ 2

Author(s):

R.D. Chamberlain ◽

M.A. Franklin

Keyword(s):

Discrete Event Simulation ◽

Discrete Event ◽

Event Simulation

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Automatic modeling of switch-level networks using partial orders

[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers ◽

10.1109/iccad.1988.122526 ◽

2003 ◽

Cited By ~ 2

Author(s):

P. Agrawal ◽

S.H. Robinson ◽

T.G. Szymanski

Keyword(s):

Partial Orders ◽

Automatic Modeling

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A tool for hierarchical test generation

[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers ◽

10.1109/iccad.1988.122541 ◽

2003 ◽

Cited By ~ 4

Author(s):

G. Kruger

Keyword(s):

Test Generation

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PACE: a parallel VLSI extractor on the Intel hypercube multiprocessor

[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers ◽

10.1109/iccad.1988.122521 ◽

2003 ◽

Cited By ~ 2

Author(s):

K.P. Belkhale ◽

P. Banerjee

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iEDISON: an interactive statistical design tool for MOS VLSI circuits

[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers ◽

10.1109/iccad.1988.122454 ◽

2003 ◽

Cited By ~ 11

Author(s):

T.K. Yu ◽

S.M. Kang ◽

I.N. Hajj ◽

T.N. Trick

Keyword(s):

Statistical Design ◽

Vlsi Circuits ◽

Design Tool

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Automatic synthesis and technology mapping of combinational logic

[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers ◽

10.1109/iccad.1988.122550 ◽

2003 ◽

Cited By ~ 3

Author(s):

R.A. Bergamaschi

Keyword(s):

Technology Mapping ◽

Combinational Logic ◽

Automatic Synthesis

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Technology mapping for standard-cell generators

[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers ◽

10.1109/iccad.1988.122551 ◽

2003 ◽

Cited By ~ 27

Author(s):

M.R.C.M. Berkelaar ◽

J.A.G. Jess

Keyword(s):

Technology Mapping ◽

Standard Cell

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Timing optimization of combinational logic

[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers ◽

10.1109/iccad.1988.122511 ◽

2003 ◽

Cited By ~ 86

Author(s):

K.J. Singh ◽

A.R. Wang ◽

R.K. Brayton ◽

A. Sangiovanni-Vincentelli

Keyword(s):

Combinational Logic ◽

Timing Optimization

Download Full-text

[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical PapersLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc. Press

CHAMP: concurrent hierarchical and multilevel program for simulation of VLSI circuits

Compaction of ATPG-generated test sequences for sequential circuits

Discrete-event simulation on hypercube architectures

Automatic modeling of switch-level networks using partial orders

A tool for hierarchical test generation

PACE: a parallel VLSI extractor on the Intel hypercube multiprocessor

iEDISON: an interactive statistical design tool for MOS VLSI circuits

Automatic synthesis and technology mapping of combinational logic

Technology mapping for standard-cell generators

Timing optimization of combinational logic

[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers
Latest Publications