Digest of Papers. 1992 IEEE VLSI Test Symposium
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Optimum redundancy design for new-generation EPROMs based on yield analysis of previous generation

Digest of Papers. 1992 IEEE VLSI Test Symposium ◽

10.1109/vtest.1992.232746 ◽

2003 ◽

Author(s):

K. Imamiya ◽

J. Miyamoto ◽

N. Ohtuska ◽

N. Tomita ◽

Y. Iyama

Keyword(s):

Yield Analysis ◽

Previous Generation ◽

Redundancy Design ◽

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Analysis of the die test optimization algorithm for negative binomial yield statistics

Digest of Papers. 1992 IEEE VLSI Test Symposium ◽

10.1109/vtest.1992.232745 ◽

2003 ◽

Author(s):

C.M. Krishna ◽

A.D. Singh

Keyword(s):

Optimization Algorithm ◽

Negative Binomial ◽

Test Optimization

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Behavior of faulty single BJT BiCMOS logic gates

Digest of Papers. 1992 IEEE VLSI Test Symposium ◽

10.1109/vtest.1992.232772 ◽

2003 ◽

Author(s):

S.M. Menon ◽

Y.K. Malaiya ◽

A.P. Jayasumana

Keyword(s):

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Simulation of physical faults in VLSI circuits

Digest of Papers. 1992 IEEE VLSI Test Symposium ◽

10.1109/vtest.1992.232750 ◽

2003 ◽

Author(s):

I.N. Hajj ◽

T. Lee

Keyword(s):

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On-chip current sensing circuit for CMOS VLSI

Digest of Papers. 1992 IEEE VLSI Test Symposium ◽

10.1109/vtest.1992.232771 ◽

2003 ◽

Author(s):

Tung-Li Shen ◽

J.C. Daly ◽

Jien-Chung Lo

Keyword(s):

Current Sensing ◽

On Chip ◽

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Hierarchical fault modeling for analog and mixed-signal circuits

Digest of Papers. 1992 IEEE VLSI Test Symposium ◽

10.1109/vtest.1992.232731 ◽

2003 ◽

Author(s):

N. Nagi ◽

J.A. Abraham

Keyword(s):

Fault Modeling ◽

Mixed Signal ◽

Mixed Signal Circuits

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Recent advances in BIST

Digest of Papers. 1992 IEEE VLSI Test Symposium ◽

10.1109/vtest.1992.232758 ◽

2003 ◽

Author(s):

S.K. Gupta

Keyword(s):

Recent Advances

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Built-in self-diagnostic by space-time compression of test responses

Digest of Papers. 1992 IEEE VLSI Test Symposium ◽

10.1109/vtest.1992.232740 ◽

2003 ◽

Author(s):

M.G. Karpovsky ◽

S.M. Chaudhry

Keyword(s):

Time Compression

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BIST linear generator based on complemented outputs

Digest of Papers. 1992 IEEE VLSI Test Symposium ◽

10.1109/vtest.1992.232738 ◽

2003 ◽

Author(s):

L.F.C. Lew Yan Voon ◽

C. Dufaza ◽

C. Landrault

Keyword(s):

Linear Generator

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A methodology for the insertion of a hierarchical and boundary-scan compatible self test

Digest of Papers. 1992 IEEE VLSI Test Symposium ◽

10.1109/vtest.1992.232721 ◽

2003 ◽

Author(s):

O.F. Haberl ◽

T. Kropf

Keyword(s):

Boundary Scan ◽

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