Low Power Networks-on-Chip
Latest Publications

TOTAL DOCUMENTS

10

(FIVE YEARS 0)

H-INDEX

2

(FIVE YEARS 0)

Published By Springer US

9781441969101, 9781441969118

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Adaptive Data Compression for Low-Power On-Chip Networks

Low Power Networks-on-Chip ◽

10.1007/978-1-4419-6911-8_6 ◽

2010 ◽

pp. 151-174

Author(s):

Yuho Jin ◽

Ki Hwan Yum ◽

Eun Jung Kim

Keyword(s):

Low Power ◽

Data Compression ◽

On Chip

Run-Time Power-Gating Techniques for Low-Power On-Chip Networks

Low Power Networks-on-Chip ◽

10.1007/978-1-4419-6911-8_2 ◽

2010 ◽

pp. 21-43

Author(s):

Hiroki Matsutani ◽

Michihiro Koibuchi ◽

Hiroshi Nakamura ◽

Hideharu Amano

Keyword(s):

Low Power ◽

Power Gating ◽

Run Time ◽

On Chip

CMOS Nanophotonics: Technology, System Implications, and a CMP Case Study

Low Power Networks-on-Chip ◽

10.1007/978-1-4419-6911-8_9 ◽

2010 ◽

pp. 223-254

Author(s):

Jung Ho Ahn ◽

Raymond G. Beausoleil ◽

Nathan Binkert ◽

Al Davis ◽

Marco Fiorentino ◽

...

Keyword(s):

Technology System

Asynchronous Communications for NoCs

Low Power Networks-on-Chip ◽

10.1007/978-1-4419-6911-8_4 ◽

2010 ◽

pp. 71-109

Author(s):

Stanislavs Golubcovs ◽

Alex Yakovlev

Keyword(s):

Asynchronous Communications

Hybrid Circuit/Packet Switched Network for Energy Efficient on-Chip Interconnections

Low Power Networks-on-Chip ◽

10.1007/978-1-4419-6911-8_1 ◽

2010 ◽

pp. 3-20 ◽

Cited By ~ 2

Author(s):

Mark A. Anders ◽

Himanshu Kaul ◽

Ram K. Krishnamurthy ◽

Shekhar Y. Borkar

Keyword(s):

Energy Efficient ◽

Switched Network ◽

On Chip ◽

Hybrid Circuit

Latency-Constrained, Power-Optimized NoC Design for a 4G SoC: A Case Study

Low Power Networks-on-Chip ◽

10.1007/978-1-4419-6911-8_7 ◽

2010 ◽

pp. 175-195

Author(s):

Rudy Beraha ◽

Isask’har Walter ◽

Israel Cidon ◽

Avinoam Kolodny

Adaptive Voltage Control for Energy-Efficient NoC Links

Low Power Networks-on-Chip ◽

10.1007/978-1-4419-6911-8_3 ◽

2010 ◽

pp. 45-69

Author(s):

Paul Ampadu ◽

Bo Fu ◽

David Wolpert ◽

Qiaoyan Yu

Keyword(s):

Energy Efficient ◽

Voltage Control

Design and Analysis of NoCs for Low-Power 2D and 3D SoCs

Low Power Networks-on-Chip ◽

10.1007/978-1-4419-6911-8_8 ◽

2010 ◽

pp. 199-222

Author(s):

Ciprian Seiculescu ◽

Srinivasan Murali ◽

Luca Benini ◽

Giovanni De Micheli

Keyword(s):

Low Power ◽

2D And 3D

RF-Interconnect for Future Network-On-Chip

Low Power Networks-on-Chip ◽

10.1007/978-1-4419-6911-8_10 ◽

2010 ◽

pp. 255-280 ◽

Cited By ~ 9

Author(s):

Sai-Wang Tam ◽

Eran Socher ◽

Mau-Chung Frank Chang ◽

Jason Cong ◽

Glenn D. Reinman

Keyword(s):

Network On Chip ◽

On Chip

Application-Specific Routing Algorithms for Low Power Network on Chip Design

Low Power Networks-on-Chip ◽

10.1007/978-1-4419-6911-8_5 ◽

2010 ◽

pp. 113-150 ◽

Cited By ~ 2

Author(s):

Maurizio Palesi ◽

Rickard Holsmark ◽

Shashi Kumar ◽

Vincenzo Catania

Keyword(s):

Low Power ◽

Network On Chip ◽

Routing Algorithms ◽

Power Network ◽

Chip Design ◽

On Chip ◽

Application Specific