2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)

Centralized traffic monitoring for online-resizable clusters in Networks-on-Chip

2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) ◽

10.1109/recosoc.2013.6581523 ◽

2013 ◽

Cited By ~ 2

Author(s):

Philipp Gorski ◽

Dirk Timmermann

Keyword(s):

Traffic Monitoring ◽

Networks On Chip ◽

On Chip

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A parallelization methodology for reconfigurable systems applied to edge detection

2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) ◽

10.1109/recosoc.2013.6581546 ◽

2013 ◽

Author(s):

Juan M. Campos ◽

Rene Cumplido ◽

Claudia Feregrino-Uribe ◽

Roberto Perez-Andrade

Keyword(s):

Edge Detection ◽

Reconfigurable Systems

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Register allocation for high-level synthesis of hardware accelerators targeting FPGAs

2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) ◽

10.1109/recosoc.2013.6581522 ◽

2013 ◽

Cited By ~ 1

Author(s):

Gerald Hempel ◽

Jan Hoyer ◽

Thilo Pionteck ◽

Christian Hochberger

Keyword(s):

Register Allocation ◽

High Level Synthesis ◽

Hardware Accelerators ◽

High Level

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An exploration of heterogeneous systems

2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) ◽

10.1109/recosoc.2013.6581542 ◽

2013 ◽

Cited By ~ 5

Author(s):

Jesus Carabano ◽

Francisco Dios ◽

Masoud Daneshtalab ◽

Masoumeh Ebrahimi

Keyword(s):

Heterogeneous Systems

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D-RECS: A complete methodology to implement Self Dynamic Reconfigurable FPGA-based systems

2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) ◽

10.1109/recosoc.2013.6581550 ◽

2013 ◽

Cited By ~ 1

Author(s):

F. Cancare ◽

C. Pilato ◽

A. Cazzaniga ◽

D. Sciuto ◽

M. D. Santambrogio

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An efficient on-chip configuration infrastructure for a flexible multi-ASIP turbo decoder architecture

2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) ◽

10.1109/recosoc.2013.6581518 ◽

2013 ◽

Author(s):

Vianney Lapotre ◽

Michael Hubner ◽

Guy Gogniat ◽

Purushotham Murugappa ◽

Amer Baghdadi ◽

...

Keyword(s):

Turbo Decoder ◽

Decoder Architecture ◽

On Chip

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Memory allocation and optimization in system-level architectural synthesis

2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) ◽

10.1109/recosoc.2013.6581537 ◽

2013 ◽

Cited By ~ 2

Author(s):

Shuo Li ◽

Ahmed Hemani

Keyword(s):

System Level ◽

Memory Allocation ◽

Architectural Synthesis

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Exploiting FPGA block memories for protected cryptographic implementations

2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) ◽

10.1109/recosoc.2013.6581529 ◽

2013 ◽

Cited By ~ 7

Author(s):

Shivam Bhasin ◽

Wei He ◽

Sylvain Guilley ◽

Jean-Luc Danger

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A new model for estimating bit error probabilities of Ring-Oscillator PUFs

2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) ◽

10.1109/recosoc.2013.6581531 ◽

2013 ◽

Cited By ~ 3

Author(s):

Matthias Hiller ◽

Georg Sigl ◽

Michael Pehl

Keyword(s):

Ring Oscillator ◽

New Model ◽

Error Probabilities

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Practical measurements of data path delays for IP authentication & integrity verification

2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) ◽

10.1109/recosoc.2013.6581551 ◽

2013 ◽

Cited By ~ 9

Author(s):

Ingrid Exurville ◽

Jacques Fournier ◽

Jean-Max Dutertre ◽

Bruno Robisson ◽

Assia Tria

Keyword(s):

Data Path ◽

Integrity Verification

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2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Centralized traffic monitoring for online-resizable clusters in Networks-on-Chip

A parallelization methodology for reconfigurable systems applied to edge detection

Register allocation for high-level synthesis of hardware accelerators targeting FPGAs

An exploration of heterogeneous systems

D-RECS: A complete methodology to implement Self Dynamic Reconfigurable FPGA-based systems

An efficient on-chip configuration infrastructure for a flexible multi-ASIP turbo decoder architecture

Memory allocation and optimization in system-level architectural synthesis

Exploiting FPGA block memories for protected cryptographic implementations

A new model for estimating bit error probabilities of Ring-Oscillator PUFs

Practical measurements of data path delays for IP authentication & integrity verification

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2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Centralized traffic monitoring for online-resizable clusters in Networks-on-Chip

A parallelization methodology for reconfigurable systems applied to edge detection

Register allocation for high-level synthesis of hardware accelerators targeting FPGAs

An exploration of heterogeneous systems

D-RECS: A complete methodology to implement Self Dynamic Reconfigurable FPGA-based systems

An efficient on-chip configuration infrastructure for a flexible multi-ASIP turbo decoder architecture

Memory allocation and optimization in system-level architectural synthesis

Exploiting FPGA block memories for protected cryptographic implementations

A new model for estimating bit error probabilities of Ring-Oscillator PUFs

Practical measurements of data path delays for IP authentication & integrity verification

2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)
Latest Publications