Proceedings of the 9th workshop on MEmory performance DEaling with Applications, systems and architecture - MEDEA '08
Latest Publications

TOTAL DOCUMENTS

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By ACM Press

9781605582436

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Zero loads

Proceedings of the 9th workshop on MEmory performance DEaling with Applications, systems and architecture - MEDEA '08 ◽

10.1145/1509084.1509087 ◽

2008 ◽

Cited By ~ 1

Author(s):

Mafijul Md. Islam ◽

Per Stenstrom

Download Full-text

A shared cache for a chip multi vector processor

Proceedings of the 9th workshop on MEmory performance DEaling with Applications, systems and architecture - MEDEA '08 ◽

10.1145/1509084.1509088 ◽

2008 ◽

Cited By ~ 7

Author(s):

Akihiro Musa ◽

Yoshiei Sato ◽

Takashi Soga ◽

Koki Okabe ◽

Ryusuke Egawa ◽

...

Keyword(s):

Vector Processor ◽

Shared Cache

Download Full-text

Accurate system-level performance modeling and workload characterization for mobile internet devices

Proceedings of the 9th workshop on MEmory performance DEaling with Applications, systems and architecture - MEDEA '08 ◽

10.1145/1509084.1509092 ◽

2008 ◽

Cited By ~ 3

Author(s):

Mitchell Hayenga ◽

Chander Sudanthi ◽

Mrinmoy Ghosh ◽

Prakash Ramrakhyani ◽

Nigel Paver

Keyword(s):

Performance Modeling ◽

Mobile Internet ◽

System Level ◽

Workload Characterization ◽

Level Performance

Download Full-text

A leakage-aware cache sharing technique for low-power chip multi-processors (CMPs) with private L2 caches

Proceedings of the 9th workshop on MEmory performance DEaling with Applications, systems and architecture - MEDEA '08 ◽

10.1145/1509084.1509089 ◽

2008 ◽

Author(s):

Hyunhee Kim ◽

Sungjun Youn ◽

Jihong Kim

Keyword(s):

Low Power

Download Full-text

Exploiting multithreaded architectures to improve the hash join operation

Proceedings of the 9th workshop on MEmory performance DEaling with Applications, systems and architecture - MEDEA '08 ◽

10.1145/1509084.1509091 ◽

2008 ◽

Cited By ~ 1

Author(s):

Layali Rashid ◽

Wessam M. Hassanein ◽

Moustafa A. Hammad

Keyword(s):

Multithreaded Architectures ◽

Hash Join

Download Full-text

Predictable dynamic instruction scratchpad for simultaneous multithreaded processors

Proceedings of the 9th workshop on MEmory performance DEaling with Applications, systems and architecture - MEDEA '08 ◽

10.1145/1509084.1509090 ◽

2008 ◽

Cited By ~ 15

Author(s):

Stefan Metzlaff ◽

Sascha Uhrig ◽

Jörg Mische ◽

Theo Ungerer

Keyword(s):

Multithreaded Processors

Download Full-text

Version management alternatives for hardware transactional memory

Proceedings of the 9th workshop on MEmory performance DEaling with Applications, systems and architecture - MEDEA '08 ◽

10.1145/1509084.1509094 ◽

2008 ◽

Cited By ~ 9

Author(s):

Marc Lupon ◽

Grigorios Magklis ◽

Antonio González

Keyword(s):

Transactional Memory ◽

Version Management ◽

Hardware Transactional Memory ◽

Management Alternatives

Download Full-text

PFetch

Proceedings of the 9th workshop on MEmory performance DEaling with Applications, systems and architecture - MEDEA '08 ◽

10.1145/1509084.1509085 ◽

2008 ◽

Cited By ~ 2

Author(s):

Jaydeep Marathe ◽

Frank Mueller

Download Full-text

Modeling of cache access behavior based on Zipf's law

Proceedings of the 9th workshop on MEmory performance DEaling with Applications, systems and architecture - MEDEA '08 ◽

10.1145/1509084.1509086 ◽

2008 ◽

Cited By ~ 6

Author(s):

Isao Kotera ◽

Ryusuke Egawa ◽

Hiroyuki Takizawa ◽

Hiroaki Kobayashi

Keyword(s):

Zipf’S Law ◽

Zipf's Law ◽

Cache Access ◽

Behavior Based

Download Full-text

WormBench

Proceedings of the 9th workshop on MEmory performance DEaling with Applications, systems and architecture - MEDEA '08 ◽

10.1145/1509084.1509093 ◽

2008 ◽

Cited By ~ 8

Author(s):

Ferad Zyulkyarov ◽

Adrian Cristal ◽

Sanja Cvijic ◽

Eduard Ayguade ◽

Mateo Valero ◽

...

Download Full-text

Proceedings of the 9th workshop on MEmory performance DEaling with Applications, systems and architecture - MEDEA '08Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By ACM Press

Zero loads

A shared cache for a chip multi vector processor

Accurate system-level performance modeling and workload characterization for mobile internet devices

A leakage-aware cache sharing technique for low-power chip multi-processors (CMPs) with private L2 caches

Exploiting multithreaded architectures to improve the hash join operation

Predictable dynamic instruction scratchpad for simultaneous multithreaded processors

Version management alternatives for hardware transactional memory

PFetch

Modeling of cache access behavior based on Zipf's law

WormBench

Proceedings of the 9th workshop on MEmory performance DEaling with Applications, systems and architecture - MEDEA '08
Latest Publications