Proceedings of the 9th workshop on MEmory performance DEaling with Applications, systems and architecture - MEDEA '08
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9781605582436

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Zero loads

Proceedings of the 9th workshop on MEmory performance DEaling with Applications, systems and architecture - MEDEA '08 ◽

10.1145/1509084.1509087 ◽

2008 ◽

Cited By ~ 1

Author(s):

Mafijul Md. Islam ◽

Per Stenstrom

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A shared cache for a chip multi vector processor

Proceedings of the 9th workshop on MEmory performance DEaling with Applications, systems and architecture - MEDEA '08 ◽

10.1145/1509084.1509088 ◽

2008 ◽

Cited By ~ 7

Author(s):

Akihiro Musa ◽

Yoshiei Sato ◽

Takashi Soga ◽

Koki Okabe ◽

Ryusuke Egawa ◽

...

Keyword(s):

Vector Processor ◽

Shared Cache

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A leakage-aware cache sharing technique for low-power chip multi-processors (CMPs) with private L2 caches

Proceedings of the 9th workshop on MEmory performance DEaling with Applications, systems and architecture - MEDEA '08 ◽

10.1145/1509084.1509089 ◽

2008 ◽

Author(s):

Hyunhee Kim ◽

Sungjun Youn ◽

Jihong Kim

Keyword(s):

Low Power

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Accurate system-level performance modeling and workload characterization for mobile internet devices

Proceedings of the 9th workshop on MEmory performance DEaling with Applications, systems and architecture - MEDEA '08 ◽

10.1145/1509084.1509092 ◽

2008 ◽

Cited By ~ 3

Author(s):

Mitchell Hayenga ◽

Chander Sudanthi ◽

Mrinmoy Ghosh ◽

Prakash Ramrakhyani ◽

Nigel Paver

Keyword(s):

Performance Modeling ◽

Mobile Internet ◽

System Level ◽

Workload Characterization ◽

Level Performance

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Exploiting multithreaded architectures to improve the hash join operation

Proceedings of the 9th workshop on MEmory performance DEaling with Applications, systems and architecture - MEDEA '08 ◽

10.1145/1509084.1509091 ◽

2008 ◽

Cited By ~ 1

Author(s):

Layali Rashid ◽

Wessam M. Hassanein ◽

Moustafa A. Hammad

Keyword(s):

Multithreaded Architectures ◽

Hash Join

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Predictable dynamic instruction scratchpad for simultaneous multithreaded processors

Proceedings of the 9th workshop on MEmory performance DEaling with Applications, systems and architecture - MEDEA '08 ◽

10.1145/1509084.1509090 ◽

2008 ◽

Cited By ~ 15

Author(s):

Stefan Metzlaff ◽

Sascha Uhrig ◽

Jörg Mische ◽

Theo Ungerer

Keyword(s):

Multithreaded Processors

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PFetch

Proceedings of the 9th workshop on MEmory performance DEaling with Applications, systems and architecture - MEDEA '08 ◽

10.1145/1509084.1509085 ◽

2008 ◽

Cited By ~ 2

Author(s):

Jaydeep Marathe ◽

Frank Mueller

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Version management alternatives for hardware transactional memory

Proceedings of the 9th workshop on MEmory performance DEaling with Applications, systems and architecture - MEDEA '08 ◽

10.1145/1509084.1509094 ◽

2008 ◽

Cited By ~ 9

Author(s):

Marc Lupon ◽

Grigorios Magklis ◽

Antonio González

Keyword(s):

Transactional Memory ◽

Version Management ◽

Hardware Transactional Memory ◽

Management Alternatives

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Evaluation of memory performance on the cell BE with the SARC programming model

Proceedings of the 9th workshop on MEmory performance DEaling with Applications, systems and architecture - MEDEA '08 ◽

10.1145/1509084.1509095 ◽

2008 ◽

Cited By ~ 4

Author(s):

Roger Ferrer ◽

Marc González ◽

Federico Silla ◽

Xavier Martorell ◽

Eduard Ayguadé

Keyword(s):

Programming Model ◽

Memory Performance

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WormBench

Proceedings of the 9th workshop on MEmory performance DEaling with Applications, systems and architecture - MEDEA '08 ◽

10.1145/1509084.1509093 ◽

2008 ◽

Cited By ~ 8

Author(s):

Ferad Zyulkyarov ◽

Adrian Cristal ◽

Sanja Cvijic ◽

Eduard Ayguade ◽

Mateo Valero ◽

...

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Proceedings of the 9th workshop on MEmory performance DEaling with Applications, systems and architecture - MEDEA '08Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By ACM Press

Zero loads

A shared cache for a chip multi vector processor

A leakage-aware cache sharing technique for low-power chip multi-processors (CMPs) with private L2 caches

Accurate system-level performance modeling and workload characterization for mobile internet devices

Exploiting multithreaded architectures to improve the hash join operation

Predictable dynamic instruction scratchpad for simultaneous multithreaded processors

PFetch

Version management alternatives for hardware transactional memory

Evaluation of memory performance on the cell BE with the SARC programming model

WormBench

Proceedings of the 9th workshop on MEmory performance DEaling with Applications, systems and architecture - MEDEA '08
Latest Publications