System-on-Chip Test Architectures
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23

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3

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Published By Elsevier

9780123739735

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Index

System-on-Chip Test Architectures ◽

10.1016/b978-012373973-5.50023-1 ◽

2008 ◽

pp. 833-856

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Software-Based Self-Testing

System-on-Chip Test Architectures ◽

10.1016/b978-012373973-5.50016-4 ◽

2008 ◽

pp. 505-548

Author(s):

Jiun-Lang Huang ◽

Kwang-Ting (Tim)

Keyword(s):

Self Testing

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Delay Testing

System-on-Chip Test Architectures ◽

10.1016/b978-012373973-5.50011-5 ◽

2008 ◽

pp. 263-306 ◽

Cited By ~ 1

Author(s):

Duncan M. (Hank) Walker ◽

Michael S. Hsiao

Keyword(s):

Delay Testing

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Fault-Tolerant Design

System-on-Chip Test Architectures ◽

10.1016/b978-012373973-5.50008-5 ◽

2008 ◽

pp. 123-170

Author(s):

Nur A. Touba

Keyword(s):

Fault Tolerant ◽

Fault Tolerant Design

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Digital Test Architectures

System-on-Chip Test Architectures ◽

10.1016/b978-012373973-5.50007-3 ◽

2008 ◽

pp. 41-121 ◽

Cited By ~ 5

Author(s):

Laung-Terng (L.-T.) Wang

Keyword(s):

Digital Test

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Field Programmable Gate Array Testing

System-on-Chip Test Architectures ◽

10.1016/b978-012373973-5.50017-6 ◽

2008 ◽

pp. 549-590

Author(s):

Charles E. Stroud

Keyword(s):

Field Programmable Gate Array ◽

Field Programmable ◽

Gate Array ◽

Array Testing

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Testing Aspects of Nanotechnology Trends

System-on-Chip Test Architectures ◽

10.1016/b978-012373973-5.50022-x ◽

2008 ◽

pp. 791-831

Author(s):

Mehdi B. Tahoori ◽

Niraj K. Jha ◽

R. Iris Bahar

Keyword(s):

Nanotechnology Trends

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Coping with Physical Failures, Soft Errors, and Reliability Issues

System-on-Chip Test Architectures ◽

10.1016/b978-012373973-5.50013-9 ◽

2008 ◽

pp. 351-422

Author(s):

Laung-Terng (L.-T.) Wang ◽

Mehrdad Nourani ◽

T.M. Mak

Keyword(s):

Soft Errors

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Acknowledgments

System-on-Chip Test Architectures ◽

10.1016/b978-012373973-5.50003-6 ◽

2008 ◽

pp. xxix-xxx

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Design for Debug and Diagnosis

System-on-Chip Test Architectures ◽

10.1016/b978-012373973-5.50015-2 ◽

2008 ◽

pp. 463-504

Author(s):

T.M. Mak ◽

Srikanth Venkataraman

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