Elastic-DF: Scaling Performance of DNN Inference in FPGA Clouds through Automatic Partitioning

Customized compute acceleration in the datacenter is key to the wider roll-out of applications based on deep neural network (DNN) inference. In this article, we investigate how to maximize the performance and scalability of field-programmable gate array (FPGA)-based pipeline dataflow DNN inference accelerators (DFAs) automatically on computing infrastructures consisting of multi-die, network-connected FPGAs. We present Elastic-DF, a novel resource partitioning tool and associated FPGA runtime infrastructure that integrates with the DNN compiler FINN. Elastic-DF allocates FPGA resources to DNN layers and layers to individual FPGA dies to maximize the total performance of the multi-FPGA system. In the resulting Elastic-DF mapping, the accelerator may be instantiated multiple times, and each instance may be segmented across multiple FPGAs transparently, whereby the segments communicate peer-to-peer through 100 Gbps Ethernet FPGA infrastructure, without host involvement. When applied to ResNet-50, Elastic-DF provides a 44% latency decrease on Alveo U280. For MobileNetV1 on Alveo U200 and U280, Elastic-DF enables a 78% throughput increase, eliminating the performance difference between these cards and the larger Alveo U250. Elastic-DF also increases operating frequency in all our experiments, on average by over 20%. Elastic-DF therefore increases performance portability between different sizes of FPGA and increases the critical throughput per cost metric of datacenter inference.

A Real-Time Deep Learning OFDM Receiver

Machine learning in the physical layer of communication systems holds the potential to improve performance and simplify design methodology. Many algorithms have been proposed; however, the model complexity is often unfeasible for real-time deployment. The real-time processing capability of these systems has not been proven yet. In this work, we propose a novel, less complex, fully connected neural network to perform channel estimation and signal detection in an orthogonal frequency division multiplexing system. The memory requirement, which is often the bottleneck for fully connected neural networks, is reduced by ≈ 27 times by applying known compression techniques in a three-step training process. Extensive experiments were performed for pruning and quantizing the weights of the neural network detector. Additionally, Huffman encoding was used on the weights to further reduce memory requirements. Based on this approach, we propose the first field-programmable gate array based, real-time capable neural network accelerator, specifically designed to accelerate the orthogonal frequency division multiplexing detector workload. The accelerator is synthesized for a Xilinx RFSoC field-programmable gate array, uses small-batch processing to increase throughput, efficiently supports branching neural networks, and implements superscalar Huffman decoders.

Performance of the ATLAS Level-1 topological trigger in Run 2

During LHC Run 2 (2015–2018) the ATLAS Level-1 topological trigger allowed efficient data-taking by the ATLAS experiment at luminosities up to 2.1$$\times $$ × 10$$^{34}$$ 34 cm$$^{-2}$$ - 2 s$$^{-1}$$ - 1 , which exceeds the design value by a factor of two. The system was installed in 2016 and operated in 2017 and 2018. It uses Field Programmable Gate Array processors to select interesting events by placing kinematic and angular requirements on electromagnetic clusters, jets, $$\tau $$ τ -leptons, muons and the missing transverse energy. It allowed to significantly improve the background event rejection and signal event acceptance, in particular for Higgs and B-physics processes.

GERARD: GEneral RApid Resolution of Digital Mazes Using a Memristor Emulator

Memristive technology is a promising game-changer in computers and electronics. In this paper, a system exploring the optimal paths through a maze, utilizing a memristor-based setup, is developed and concreted on a FPGA (field-programmable gate array) device. As a memristor, a digital emulator has been used. According to the proposed approach, the memristor is used as a delay element, further configuring the test graph as a memristor network. A parallel algorithm is then applied, successfully reducing computing time and increasing the system’s efficiency. The proposed system is simple, easy to scale up and capable of implementing different graph configurations. The operation of the algorithm in the MATLAB (matrix laboratory) programming enviroment is checked beforehand and then exported to two different Intel FPGAs: a DE0-Nano board and an Arria 10 GX 220 FPGA. In both cases, reliable results are obtained quickly and conveniently, even for the case of a 300 × 300 nodes maze.

Một giải pháp quản lý kết nối mật cho IPSec trên FPGA

Tóm tắt—IPSec (Internet Protocol Security) là bộ giao thức an toàn nhằm bảo vệlưu lượng dữ liệu qua mạng Internet. Mỗi kết nối mật trong mô hình triển khai IPSec có một bộ thuật toán, tham số bảo mật riêng. Để đảm bảo các kết nối mật hoạt động ổn định trong môi trường truyền tin với băng thông lớn, việc quản lý nhiều kết nối mật đồng thời trên thiết bị IPSec đóng vai trò vô cùng quan trọng. Do tính phức tạp của quá trình quản lý, thông thường vấn đề này được thực hiện bằng phần mềm trên hệđiều hành. Giải pháp này bị hạn chế do quá trình trao đổi dữ liệu giữavi mạch Field Programmable Gate Array (FPGA) và bộ vi xử lý. Trong bài viết này, nhóm tác giả đưa ra một giải pháp tổ chức, quản lý kết nối mật sau khi sử dụng giao thức Internet Key Exchange (IKE) để trao đổi khóa cho IPSec trên FPGA sử dụng ngôn ngữ mô tả phần cứng, nhằm đáp ứng yêu cầu tốc độ cao với nhiều kết nối.Abstract—IPSec (Internet Protocol Security) is a secure protocol aiming to protect data traffic via the Internet. There is a separate set of algorithms and security parameters in each secure connection in the IPSec deployment model. In order to ensure stable connections in high-bandwidth environments, managing multiple secure connections simultaneously on IPSec devices holds a significant role. Due to the complexity of the management process, this is commonly done by software on the operating system. This solution is restricted due to data exchange between field-programmable gate array (FPGA) and microprocessor. In this article, a solution was proposed to organize and manage a confidential connection after using Internet Key Exchange (IKE) to exchange keys for IPSec directly using hardware description language on FPGA, aiming to meet high-speed requirements with many connections.

Xây dựng giải pháp trao đổi khóa IKEv2 sử dụng NIOS II trên FPGA

Tóm tắt—Giao thức Internet Key Exchange (IKE) là một giao thức thực hiện quá trình trao đổi khóa và thỏa thuận trong chế độ bảo mật IPSec. Để thực thi giao thức bảo mật IPSec tốc độ cao thì thường kết hợp giữa phần mềm và phần cứng trên vi mạch Field Programmable Gate Array (FPGA) [7], [8]. Trong đó, các thao tác mật mã, đóng gói và bóc tách gói tin được thực hiện bằng FPGA để đảm bảo thực hiện hệ thống IPSec tốc độ cao; giao thức trao đổi khóa IKE được thực hiện bằng phần mềm sử dụng hệ điều hành Linux nhúng. Trong bài báo này, nhóm tác giả giới thiệu giải pháp thực hiện giải thuật trao đổi khóa IKE sử dụng Nios II trên FPGA. Với cách tiếp cận này, nhóm tác giả đã tự tổ chức, xây dựng chương trình trên bộ vi xử lý, nhờ đó kiểm soát được toàn bộ dòng dữ liệu. Abstract—IKE (Internet Key Exchange) is a protocol that performs key exchange and agreement process in IPSec security mode. To implement high speed IPSec security protocol, it is often combined software and hardware on Field Programmable Gate Array (FPGA) [7], [8]. Therein, encryption, packet encapsulation and extraction operations will be performed by FPGA to ensure high speed IPSec system implementation; the IKE protocol is implemented by software using an embed Linux operating system. In this paper, the authors introduce the solution of implementing IKE key exchange algorithm using Nios II on FPGA. With this approach, the authors have organized and built the program on the microprocessor by themselves, therefore the entire data stream is controlled.

Bubble-Proof Algorithm for Wave Union TDCs

Nowadays state-of-the-art time-to-digital converters (TDCs) are commonly implemented in field-programmable gate array (FPGA) devices using different variations of the wave union method. To take full advantage of this method many design challenges need to be overcome, one of which is an efficient data encoding. In this work, we describe in detail an effective algorithm to decode raw output data from a newly designed multisampling wave union TDC. The algorithm is able to correct bubble errors and detect any number of transitions, which occur in the wave union TDC output code. This allows us to reach a mean resolution as high as 0.39 ps and a single shot precision of 2.33 ps in the Xilinx Kintex-7 FPGA chip. The presented algorithm can be used for any kind of wave union TDCs and is intended for partial hardware implementation.

Switching between Dissipative and Conservative Behaviors in a Modified Hyperchaotic System with the Variation of Its Parameter

The paper reports a modified 4D autonomous hyperchaotic system with an unusual characteristic. The modified system exhibits dissipative behavior for some ranges of a parameter and conservative behavior for the other ranges of the same parameter. Thus, there is a switching between dissipative and conservative behaviors of the proposed system. In the conservative range, the system exhibits chaotic orbit. Again in the dissipative range, the system, with its considered sets of parameters, exhibits strange attractors. Thus, both the dissipative and conservative behaviors exist in the same system with the switching of its parameter. Such behavior of a system is rarely reported in the literature. Further, the equilibria of the system are located on the surface-shape. The proposed system is implemented and simulated using Field Programmable Gate Array (FPGA) and Multisim simulation softwares.