2009 18th International Conference on Parallel Architectures and Compilation Techniques
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48

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15

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Published By IEEE

9780769537719

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Using Aggressor Thread Information to Improve Shared Cache Management for CMPs

2009 18th International Conference on Parallel Architectures and Compilation Techniques ◽

10.1109/pact.2009.13 ◽

2009 ◽

Author(s):

Wanli Liu ◽

D. Yeung

Keyword(s):

Cache Management ◽

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FASTM: A Log-based Hardware Transactional Memory with Fast Abort Recovery

2009 18th International Conference on Parallel Architectures and Compilation Techniques ◽

10.1109/pact.2009.19 ◽

2009 ◽

Author(s):

Marc Lupon ◽

Grigorios Magklis ◽

Antonio Gonzalez

Keyword(s):

Transactional Memory ◽

Hardware Transactional Memory

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Anaphase: A Fine-Grain Thread Decomposition Scheme for Speculative Multithreading

2009 18th International Conference on Parallel Architectures and Compilation Techniques ◽

10.1109/pact.2009.27 ◽

2009 ◽

Author(s):

Carlos Madriles ◽

Pedro Lopez ◽

Josep Maria Codina ◽

Enric Gibert ◽

Fernando Latorre ◽

...

Keyword(s):

Speculative Multithreading ◽

Decomposition Scheme ◽

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Automatic Tuning of Discrete Fourier Transforms Driven by Analytical Modeling

2009 18th International Conference on Parallel Architectures and Compilation Techniques ◽

10.1109/pact.2009.11 ◽

2009 ◽

Author(s):

Basilio B. Fraguela ◽

Yevgen Voronenko ◽

Markus Puschel

Keyword(s):

Analytical Modeling ◽

Fourier Transforms ◽

Automatic Tuning ◽

Discrete Fourier Transforms

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Title Page iii

2009 18th International Conference on Parallel Architectures and Compilation Techniques ◽

10.1109/pact.2009.2 ◽

2009 ◽

Keyword(s):

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Memory Performance and Cache Coherency Effects on an Intel Nehalem Multiprocessor System

2009 18th International Conference on Parallel Architectures and Compilation Techniques ◽

10.1109/pact.2009.22 ◽

2009 ◽

Author(s):

Daniel Molka ◽

Daniel Hackenberg ◽

Robert Schone ◽

Matthias S. Muller

Keyword(s):

Memory Performance ◽

Multiprocessor System ◽

Cache Coherency

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Keynote: Why are Graphics Systems so Fast?

2009 18th International Conference on Parallel Architectures and Compilation Techniques ◽

10.1109/pact.2009.45 ◽

2009 ◽

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Algorithmic Skeletons within an Embedded Domain Specific Language for the CELL Processor

2009 18th International Conference on Parallel Architectures and Compilation Techniques ◽

10.1109/pact.2009.21 ◽

2009 ◽

Author(s):

Tarik Saidani ◽

Joel Falcou ◽

Claude Tadonki ◽

Lionel Lacassagne ◽

Daniel Etiemble

Keyword(s):

Domain Specific Language ◽

Algorithmic Skeletons ◽

Cell Processor ◽

Specific Language ◽

Domain Specific

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Core-Selectability in Chip Multiprocessors

2009 18th International Conference on Parallel Architectures and Compilation Techniques ◽

10.1109/pact.2009.44 ◽

2009 ◽

Author(s):

Hashem Hashemi Najaf-abadi ◽

Niket Kumar Choudhary ◽

Eric Rotenberg

Keyword(s):

Chip Multiprocessors

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Zero-Value Caches: Cancelling Loads that Return Zero

2009 18th International Conference on Parallel Architectures and Compilation Techniques ◽

10.1109/pact.2009.29 ◽

2009 ◽

Author(s):

Mafijul Md. Islam ◽

Per Stenstrom

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