2007 IEEE 13th International Symposium on High Performance Computer Architecture
Latest Publications

TOTAL DOCUMENTS

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(FIVE YEARS 0)

Published By IEEE

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Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

A Memory-Level Parallelism Aware Fetch Policy for SMT Processors

2007 IEEE 13th International Symposium on High Performance Computer Architecture ◽

10.1109/hpca.2007.346201 ◽

2007 ◽

Cited By ~ 15

Author(s):

Stijn Everman ◽

Lieven Eeckhout

Keyword(s):

Level Parallelism

Implications of Device Timing Variability on Full Chip Timing

2007 IEEE 13th International Symposium on High Performance Computer Architecture ◽

10.1109/hpca.2007.346183 ◽

2007 ◽

Cited By ~ 3

Author(s):

Murali Annavaram ◽

Ed Grochowski ◽

Paul Reed

Keyword(s):

Timing Variability

Conference committee

2007 IEEE 13th International Symposium on High Performance Computer Architecture ◽

10.1109/hpca.2007.346176 ◽

2007 ◽

Keyword(s):

Conference Committee

Interconnect-Centric Computing

2007 IEEE 13th International Symposium on High Performance Computer Architecture ◽

10.1109/hpca.2007.346179 ◽

2007 ◽

Cited By ~ 3

Author(s):

William J. Dally

A Domain-Specific On-Chip Network Design for Large Scale Cache Systems

2007 IEEE 13th International Symposium on High Performance Computer Architecture ◽

10.1109/hpca.2007.346209 ◽

2007 ◽

Cited By ~ 18

Author(s):

Yuho Jin ◽

Eun Jung Kim ◽

Ki Hwan Yum

Keyword(s):

Network Design ◽

Large Scale ◽

Domain Specific ◽

On Chip

A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures

2007 IEEE 13th International Symposium on High Performance Computer Architecture ◽

10.1109/hpca.2007.346194 ◽

2007 ◽

Cited By ~ 15

Author(s):

Ricardo Fernandez-Pascual ◽

Jose M. Garcia ◽

Manuel E. Acacio ◽

Jose Duato

Keyword(s):

Fault Tolerant

A Burst Scheduling Access Reordering Mechanism

2007 IEEE 13th International Symposium on High Performance Computer Architecture ◽

10.1109/hpca.2007.346206 ◽

2007 ◽

Cited By ~ 66

Author(s):

Jun Shao ◽

Brian T. Davis

Keyword(s):

Burst Scheduling

Exploiting Postdominance for Speculative Parallelization

2007 IEEE 13th International Symposium on High Performance Computer Architecture ◽

10.1109/hpca.2007.346207 ◽

2007 ◽

Cited By ~ 6

Author(s):

Mayank Agarwal ◽

Kshitiz Malik ◽

Kevin M. Woley ◽

Sam S. Stone ◽

Matthew I. Frank

Keyword(s):

Speculative Parallelization

Error Detection via Online Checking of Cache Coherence with Token Coherence Signatures

2007 IEEE 13th International Symposium on High Performance Computer Architecture ◽

10.1109/hpca.2007.346193 ◽

2007 ◽

Cited By ~ 15

Author(s):

Albert Meixner ◽

Daniel J. Sorin

Keyword(s):

Error Detection ◽

Cache Coherence

Illustrative Design Space Studies with Microarchitectural Regression Models

2007 IEEE 13th International Symposium on High Performance Computer Architecture ◽

10.1109/hpca.2007.346211 ◽

2007 ◽

Cited By ~ 59

Author(s):

Benjamin C. Lee ◽

David M. Brooks

Keyword(s):

Regression Models ◽

Design Space

2007 IEEE 13th International Symposium on High Performance Computer ArchitectureLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

A Memory-Level Parallelism Aware Fetch Policy for SMT Processors

Implications of Device Timing Variability on Full Chip Timing

Conference committee

Interconnect-Centric Computing

A Domain-Specific On-Chip Network Design for Large Scale Cache Systems

A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures

A Burst Scheduling Access Reordering Mechanism

Exploiting Postdominance for Speculative Parallelization

Error Detection via Online Checking of Cache Coherence with Token Coherence Signatures

Illustrative Design Space Studies with Microarchitectural Regression Models

2007 IEEE 13th International Symposium on High Performance Computer Architecture
Latest Publications