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Proceedings of International Workshop on Defect and Fault Tolerance in VLSI
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TOTAL DOCUMENTS
35
(FIVE YEARS 0)
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7
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Published By IEEE
0818671076
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Latest Documents
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Characterization and analysis of errors in circuit test
Proceedings of International Workshop on Defect and Fault Tolerance in VLSI
◽
10.1109/dftvs.1995.476960
◽
2002
◽
Cited By ~ 1
Author(s):
T. Ziaja
◽
E. Swartzlander
Download Full-text
AFFCCA: a tool for critical area analysis with circular defects and lithography deformed layout
Proceedings of International Workshop on Defect and Fault Tolerance in VLSI
◽
10.1109/dftvs.1995.476932
◽
2002
◽
Cited By ~ 9
Author(s):
I. Bubel
◽
W. Maly
◽
T. Waas
◽
P.K. Nag
◽
H. Hartmann
◽
...
Keyword(s):
Critical Area
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FFT-based test of a yield monitor circuit
Proceedings of International Workshop on Defect and Fault Tolerance in VLSI
◽
10.1109/dftvs.1995.476958
◽
2002
◽
Author(s):
C. Thibeault
◽
A. Payeur
Keyword(s):
Yield Monitor
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Efficient time redundancy for error correcting inner-product units and convolvers
Proceedings of International Workshop on Defect and Fault Tolerance in VLSI
◽
10.1109/dftvs.1995.476953
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2002
◽
Author(s):
Yuang-Ming Hsu
◽
V. Piuri
◽
E.E. Swartzlander
Keyword(s):
Inner Product
◽
Time Redundancy
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A model for the evaluation of fault tolerance in the FERMI system
Proceedings of International Workshop on Defect and Fault Tolerance in VLSI
◽
10.1109/dftvs.1995.476939
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2002
◽
Cited By ~ 1
Author(s):
A. Antola
◽
L. Breveglieri
Keyword(s):
Fault Tolerance
◽
Fermi System
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Efficient algorithms for analyzing and synthesizing fault-tolerant datapaths
Proceedings of International Workshop on Defect and Fault Tolerance in VLSI
◽
10.1109/dftvs.1995.476940
◽
2002
◽
Cited By ~ 4
Author(s):
R. Narasimhan
◽
D.J. Rosenkrantz
◽
S.S. Ravi
Keyword(s):
Fault Tolerant
◽
Efficient Algorithms
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Accurate yield estimation of circuits with redundancy
Proceedings of International Workshop on Defect and Fault Tolerance in VLSI
◽
10.1109/dftvs.1995.476948
◽
2002
◽
Cited By ~ 2
Author(s):
D.D. Gaitonde
◽
D.M.H. Walker
◽
W. Maly
Keyword(s):
Yield Estimation
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Approximation of critical area of ICs with simple parameters extracted from the layout
Proceedings of International Workshop on Defect and Fault Tolerance in VLSI
◽
10.1109/dftvs.1995.476931
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2002
◽
Cited By ~ 3
Author(s):
F. Duvivier
◽
M. Rivier
Keyword(s):
Critical Area
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A study of time redundant fault tolerance techniques for superscalar processors
Proceedings of International Workshop on Defect and Fault Tolerance in VLSI
◽
10.1109/dftvs.1995.476954
◽
2002
◽
Cited By ~ 32
Author(s):
M. Franklin
Keyword(s):
Fault Tolerance
◽
Superscalar Processors
◽
Redundant Fault
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Design of defect-tolerant scan chains for MCMs with an active substrate
Proceedings of International Workshop on Defect and Fault Tolerance in VLSI
◽
10.1109/dftvs.1995.476959
◽
2002
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Cited By ~ 1
Author(s):
P. Brahic
◽
R. Leveugle
◽
G. Saucier
Keyword(s):
Active Substrate
◽
Scan Chains
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