2011 IEEE International High Level Design Validation and Test Workshop
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9781457717437, 9781457717444, 9781457717420

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Sufficiency-based filtering of invariants for Sequential Equivalence Checking

2011 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2011.6114159 ◽

2011 ◽

Cited By ~ 1

Author(s):

Wei Hu ◽

Huy Nguyen ◽

Michael S. Hsiao

Keyword(s):

Equivalence Checking ◽

Sequential Equivalence Checking

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Utilizing GPGPUs for design validation with a modified Ant Colony Optimization

2011 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2011.6113988 ◽

2011 ◽

Cited By ~ 2

Author(s):

Min Li ◽

Kelson Gent ◽

Michael S. Hsiao

Keyword(s):

Ant Colony Optimization ◽

Ant Colony ◽

Design Validation

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A scalable hybrid verification system based on HDL slicing

2011 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2011.6114164 ◽

2011 ◽

Cited By ~ 3

Author(s):

Somnath Banerjee ◽

Tushar Gupta ◽

Saurabh Jain

Keyword(s):

Verification System

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UNIVERCM: The UNIversal VERsatile computational model for heterogeneous embedded system design

2011 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2011.6114163 ◽

2011 ◽

Cited By ~ 2

Author(s):

Luigi Di Guglielm ◽

Franco Fummi ◽

Graziano Pravadelli ◽

Francesco Stefanni ◽

Sara Vinco

Keyword(s):

Embedded System ◽

Computational Model ◽

System Design ◽

Embedded System Design

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Software agnostic approaches to explore pre-silicon system performance

2011 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2011.6113986 ◽

2011 ◽

Cited By ~ 4

Author(s):

Frederic Risacher ◽

Kenneth J. Schultz

Keyword(s):

System Performance ◽

Silicon System

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Cardio: Adaptive CMPs for reliability through dynamic introspective operation

2011 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2011.6113983 ◽

2011 ◽

Cited By ~ 4

Author(s):

Andrea Pellegrini ◽

Valeria Bertacco

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Formal verification guided automatic design error diagnosis and correction of complex processors

2011 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2011.6113987 ◽

2011 ◽

Cited By ~ 3

Author(s):

Amir Masoud Gharehbaghi ◽

Masahiro Fujita

Keyword(s):

Formal Verification ◽

Automatic Design ◽

Error Diagnosis ◽

Design Error

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Causality analysis of synchronous programs with refined clocks

2011 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2011.6114162 ◽

2011 ◽

Author(s):

Mike Gemunde ◽

Jens Brandt ◽

Klaus Schneider

Keyword(s):

Causality Analysis

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Interactive presentation abstract: Automated correction of design errors by edge redirection on high-level decision diagrams

2011 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2011.6113980 ◽

2011 ◽

Author(s):

Anton Karputkin ◽

Raimund Ubar ◽

Mati Tombak ◽

Jaan Raik

Keyword(s):

Decision Diagrams ◽

High Level

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Introducing XCS to Coverage Directed test Generation

2011 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2011.6114166 ◽

2011 ◽

Cited By ~ 4

Author(s):

Charalambos Ioannides ◽

Geoff Barrett ◽

Kerstin Eder

Keyword(s):

Test Generation

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2011 IEEE International High Level Design Validation and Test WorkshopLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Sufficiency-based filtering of invariants for Sequential Equivalence Checking

Utilizing GPGPUs for design validation with a modified Ant Colony Optimization

A scalable hybrid verification system based on HDL slicing

UNIVERCM: The UNIversal VERsatile computational model for heterogeneous embedded system design

Software agnostic approaches to explore pre-silicon system performance

Cardio: Adaptive CMPs for reliability through dynamic introspective operation

Formal verification guided automatic design error diagnosis and correction of complex processors

Causality analysis of synchronous programs with refined clocks

Interactive presentation abstract: Automated correction of design errors by edge redirection on high-level decision diagrams

Introducing XCS to Coverage Directed test Generation

2011 IEEE International High Level Design Validation and Test Workshop
Latest Publications