Sixth IEEE International High-Level Design Validation and Test Workshop
Latest Publications

TOTAL DOCUMENTS

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

0769514111

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Symbolic simulation techniques-state-of-the-art and applications

Sixth IEEE International High-Level Design Validation and Test Workshop ◽

10.1109/hldvt.2001.972806 ◽

2002 ◽

Cited By ~ 4

Author(s):

C. Blank ◽

H. Eveking ◽

J. Levihn ◽

G. Ritter

Keyword(s):

State Of The Art ◽

Symbolic Simulation ◽

Simulation Techniques

Download Full-text

On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault model

Sixth IEEE International High-Level Design Validation and Test Workshop ◽

10.1109/hldvt.2001.972821 ◽

2002 ◽

Author(s):

Chun-Yao Wang ◽

Shing-Wu Tung ◽

Jing-Yang Jou

Keyword(s):

Fault Model ◽

Data Path ◽

Design Verification

Download Full-text

Taylor expansion diagrams: a new representation for RTL verification

Sixth IEEE International High-Level Design Validation and Test Workshop ◽

10.1109/hldvt.2001.972810 ◽

2002 ◽

Cited By ~ 6

Author(s):

M. Ciesielski ◽

P. Kalla ◽

Zhihong Zeng ◽

B. Rouzeyre

Keyword(s):

Taylor Expansion

Download Full-text

Fast timed cosimulation of HW/SW implementation of embedded multiprocessor SoC communication

Sixth IEEE International High-Level Design Validation and Test Workshop ◽

10.1109/hldvt.2001.972811 ◽

2002 ◽

Author(s):

Sungjoo Yoo ◽

G. Nicolescu ◽

L. Gauthier ◽

A.A. Jerraya

Keyword(s):

Multiprocessor Soc

Download Full-text

Relating buffer-oriented microarchitecture validation to high-level pipeline functionality

Sixth IEEE International High-Level Design Validation and Test Workshop ◽

10.1109/hldvt.2001.972799 ◽

2002 ◽

Cited By ~ 2

Author(s):

N. Utamaphethai ◽

R.D. Blanton ◽

J.P. Shen

Keyword(s):

High Level

Download Full-text

Proving sequential consistency by model checking

Sixth IEEE International High-Level Design Validation and Test Workshop ◽

10.1109/hldvt.2001.972815 ◽

2002 ◽

Cited By ~ 2

Author(s):

T. Braun ◽

A. Condon ◽

A.J. Hu ◽

K.S. Juse ◽

M. Laza ◽

...

Keyword(s):

Model Checking ◽

Sequential Consistency

Download Full-text

Constraints specification at higher levels of abstraction

Sixth IEEE International High-Level Design Validation and Test Workshop ◽

10.1109/hldvt.2001.972819 ◽

2002 ◽

Cited By ~ 24

Author(s):

F. Balarin ◽

J. Burch ◽

L. Lavagno ◽

Y. Watanabe ◽

R. Passerone ◽

...

Keyword(s):

Levels Of Abstraction

Download Full-text

Practical use of sequential ATPG for model checking: going the extra mile does pay off

Sixth IEEE International High-Level Design Validation and Test Workshop ◽

10.1109/hldvt.2001.972805 ◽

2002 ◽

Cited By ~ 10

Author(s):

M. Hsiao ◽

J. Jain

Keyword(s):

Model Checking

Download Full-text

A language formalism for verification of PowerPC/sup TM/ custom memories using compositions of abstract specifications

Sixth IEEE International High-Level Design Validation and Test Workshop ◽

10.1109/hldvt.2001.972820 ◽

2002 ◽

Cited By ~ 4

Author(s):

J. Bhadra ◽

A. Martin ◽

J. Abraham ◽

M. Abadir

Download Full-text

An analysis of ATPG and SAT algorithms for formal verification

Sixth IEEE International High-Level Design Validation and Test Workshop ◽

10.1109/hldvt.2001.972826 ◽

2002 ◽

Cited By ~ 13

Author(s):

G. Parthasarathy ◽

Chung-Yang Huang ◽

Kwang-Ting Cheng

Keyword(s):

Formal Verification

Download Full-text

Sixth IEEE International High-Level Design Validation and Test WorkshopLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Symbolic simulation techniques-state-of-the-art and applications

On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault model

Taylor expansion diagrams: a new representation for RTL verification

Fast timed cosimulation of HW/SW implementation of embedded multiprocessor SoC communication

Relating buffer-oriented microarchitecture validation to high-level pipeline functionality

Proving sequential consistency by model checking

Constraints specification at higher levels of abstraction

Practical use of sequential ATPG for model checking: going the extra mile does pay off

A language formalism for verification of PowerPC/sup TM/ custom memories using compositions of abstract specifications

An analysis of ATPG and SAT algorithms for formal verification

Sixth IEEE International High-Level Design Validation and Test Workshop
Latest Publications