2017 IEEE 35th VLSI Test Symposium (VTS)
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9781509044825
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Special session on early life failures

2017 ◽  
Author(s):  
Jyotirmoy Deshmukh ◽  
Wolfgang Kunz ◽  
Hans-Joachim Wunderlich ◽  
Sybille Hellebrand
Keyword(s):  
Early Life ◽  
Special Session

Analysis of an efficient on-chip servo-loop technique for reduced-code static linearity test of pipeline ADCs

2017 ◽  
Author(s):  
Guillaume Renaud ◽  
Marc Margalef-Rovira ◽  
Manuel J. Barragan ◽  
Salvador Mir
Keyword(s):  
Servo Loop ◽  
Loop Technique ◽  
Pipeline Adcs ◽  
On Chip ◽  
Linearity Test

At-speed capture global noise reduction & low-power memory test architecture

2017 ◽  
Author(s):  
Bonita Bhaskaran ◽  
Sailendra Chadalavada ◽  
Shantanu Sarangi ◽  
Nithin Valentine ◽  
Venkat Abilash Reddy Nerallapally ◽  
...  
Keyword(s):  
Low Power ◽  
Noise Reduction ◽  
Memory Test ◽  
Test Architecture

Innovative practices session 4C data analytics in test

2017 ◽  
Author(s):  
Suriya Natarajan ◽  
Abhijit Sathaye
Keyword(s):  
Data Analytics

Efficient SAT-based generation of hazard-activated TSOF tests

2017 ◽  
Author(s):  
Jan Burchard ◽  
Dominik Erb ◽  
Sudhakar M. Reddy ◽  
Adit D. Singh ◽  
Bernd Becker

Dynamically obfuscated scan for protecting IPs against scan-based attacks throughout supply chain

2017 ◽  
Author(s):  
Dongrong Zhang ◽  
Miao He ◽  
Xiaoxiao Wang ◽  
Mark Tehranipoor
Keyword(s):  
Supply Chain
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