A Low Complexity Digital Foreground Calibration Technique for CMOS Pipelined ADCs

A low complexity all-digital foreground calibration technique to correct linear and nonlinear errors is proposed for pipeline ADCs in this paper. This method based on the integral nonlinearity (INL) piecewise least-squares fitting improves the linearity and obtains better SNR and SFDR performance. Two switches are added to the pre-stage reference ladder to achieve an accurate measurement of the INL and DNL of the backend ADC, which reduces the calibration complexity and improves the linearity effectively. The method was applied to a 125[Formula: see text]MS/s 14-bit pipeline ADC fabricated in a 0.18[Formula: see text][Formula: see text]m CMOS process. The raw DNL and INL were 1[Formula: see text]LSB and 8[Formula: see text]LSB, respectively, without calibration, but with calibration, they were respectively improved to 0.25[Formula: see text]LSB and 2[Formula: see text]LSB. The ADC achieved an SNR of 64.5[Formula: see text]dB, an SFDR of 73.8[Formula: see text]dB and a THD of 72.7[Formula: see text]dB with a 10[Formula: see text]MHz input signal without calibration, but after calibration these figures were improved to 72.6[Formula: see text]dB, 87.5[Formula: see text]dB and 86.6[Formula: see text]dB, respectively. Its application can also be extended to SAR ADC architecture, etc.