Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201)
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Early load address resolution via register tracking

Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201) ◽

10.1109/isca.2000.854400 ◽

2002 ◽

Cited By ~ 4

Author(s):

M. Bekeman ◽

A. Yoaz ◽

F. Gabbay ◽

S. Jourdan ◽

M. Kalaev ◽

...

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Recency-based TLB preloading

Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201) ◽

10.1109/isca.2000.854383 ◽

2002 ◽

Author(s):

A. Saulsbury ◽

F. Dahlgren ◽

P. Stenstrom

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HLS: combining statistical and symbolic simulation to guide microprocessor designs

Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201) ◽

10.1109/isca.2000.854379 ◽

2002 ◽

Cited By ~ 3

Author(s):

M. Oskin ◽

F.T. Chong ◽

M. Farrens

Keyword(s):

Symbolic Simulation

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Trace preconstruction

Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201) ◽

10.1109/isca.2000.854376 ◽

2002 ◽

Author(s):

Q. Jacobson ◽

J.E. Smith

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Lx: a technology platform for customizable VLIW embedded processing

Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201) ◽

10.1109/isca.2000.854391 ◽

2002 ◽

Cited By ~ 15

Author(s):

P. Faraboschi ◽

G. Brown ◽

J.A. Fisher ◽

G. Desoll ◽

F.M.O. Homewood

Keyword(s):

Technology Platform ◽

Embedded Processing

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Memory access scheduling

Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201) ◽

10.1109/isca.2000.854384 ◽

2002 ◽

Cited By ~ 3

Author(s):

S. Rixner ◽

W.J. Dally ◽

U.J. Kapasi ◽

P. Mattson ◽

J.D. Owens

Keyword(s):

Memory Access

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A hardware mechanism for dynamic extraction and relayout of program hot spots

Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201) ◽

10.1109/isca.2000.854378 ◽

2002 ◽

Author(s):

M.C. Merten ◽

A.R. Trick ◽

E.M. Nystrom ◽

R.D. Barnes ◽

W.-M.W. Hwu

Keyword(s):

Hot Spots ◽

Dynamic Extraction

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Reconfigurable caches and their application to media processing

Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201) ◽

10.1109/isca.2000.854392 ◽

2002 ◽

Cited By ~ 2

Author(s):

P. Ranganathan ◽

S. Adve ◽

N.P. Jouppi

Keyword(s):

Media Processing ◽

Reconfigurable Caches

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Piranha: a scalable architecture based on single-chip multiprocessing

Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201) ◽

10.1109/isca.2000.854398 ◽

2002 ◽

Cited By ~ 7

Author(s):

L.A. Barroso ◽

K. Gharachorloo ◽

R. McNamara ◽

A. Nowatzyk ◽

S. Qadeer ◽

...

Keyword(s):

Single Chip ◽

Scalable Architecture

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Transient fault detection via simultaneous multithreading

Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201) ◽

10.1109/isca.2000.854375 ◽

2002 ◽

Cited By ~ 1

Author(s):

S.K. Reinhardt ◽

S.S. Mukherjee

Keyword(s):

Fault Detection ◽

Simultaneous Multithreading ◽

Transient Fault

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Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By ACM

Early load address resolution via register tracking

Recency-based TLB preloading

HLS: combining statistical and symbolic simulation to guide microprocessor designs

Trace preconstruction

Lx: a technology platform for customizable VLIW embedded processing

Memory access scheduling

A hardware mechanism for dynamic extraction and relayout of program hot spots

Reconfigurable caches and their application to media processing

Piranha: a scalable architecture based on single-chip multiprocessing

Transient fault detection via simultaneous multithreading

Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201)
Latest Publications