media processing
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2021 ◽  
Vol 9 (2) ◽  
pp. 129-140
Author(s):  
Venkata Naga Satya Surendra Chimakurthi

The study presents the XaaS architecture and explores how this business model has strategically developed and how it has revolutionized the whole business industry. The study indicates how this particular business model allows companies to enhance the range of advantages of Internet Cloud model applications, particularly when it deals with process of media processing and customization of users. Its huge benefits with negligible disadvantages are mentioned as part of the presented research. This study will help to understand the services of XaaS model, challenges experiencing by it and its future opportunities. This will also assists new scholars of field to build a better understanding and better prospects regarding XaaS in future.


Author(s):  
Uppugunduru Anil Kumar ◽  
Syed Ershad Ahmed

Approximate computing is an attractive technique to gain substantial improvement in the area, speed, and power in applications where exact computation is not required. This paper proposes two improved multiplier designs based on a new 4:2 approximate compressor circuit to simplify the hardware at the partial product reduction stage. The proposed multiplier designs are targeted towards error-tolerant applications. Exhaustive error and hardware analysis has been carried out on the existing and proposed multiplier designs. The results prove that the proposed approximate multiplier architecture performs better than the existing architectures without significant compromise on quality metrics. Experimental results show that die-area and power consumed are reduced upto 28%, and 25.29% respectively in comparison with the existing designs without significant compromise on accuracy.


Author(s):  
Roberto Ramos-Chavez ◽  
Rufael Mekuria ◽  
Theo Karagkioules ◽  
Dirk Griffioen ◽  
Arjen Wagenaar ◽  
...  
Keyword(s):  

2021 ◽  
Vol 3 (1) ◽  
pp. 1-9
Author(s):  
Andi Yusika Rangan ◽  
Siti Qomariah ◽  
Amelia Yusnita

Public relations (public relations) are one of the processes in building the image of an institution. Social media has emerged as a flexible and informative means of communication. Social media is one of them because of features such as sharing text or writing, photos and videos. with assistance carried out in terms of making social media, processing content and publishing content on facebook, instagram and youtube, boarding school administrators can interact with the wider community, improve the image of the institution despite the limited human resources and funding with the right digital branding strategy.


2021 ◽  
pp. 1-20
Author(s):  
Jian Yuan ◽  
Zhongyu Wei ◽  
Yixu Gao ◽  
Wei Chen ◽  
Jun Song ◽  
...  

Abstract In this paper we present the results of the Interactive Argument-Pair Extraction in Judgement Document Competition held by both the Chinese AI and Law challenge (CAIL) and the Chinese National Social Media Processing Conference (SMP), and introduce the related dataset – SMP-CAIL2020-Argmine. The task challenged participants to choose the correct argument among five candidates proposed by the defense to refute or acknowledge the given argument made by the plaintiff, providing the full context recorded in the judgement documents of both parties. We received entries from 63 competing teams, 38 of which scored higher than the provided baseline model (BERT) in the first phase and entered the second phase. The best performing system in the two phases achieved accuracy of 0.856 and 0.905 respectively. In this paper, we will present the results of the competition and a summary of the systems, highlighting commonalities and innovations among participating systems. The SMP-CAIL2020-Argmine dataset and baseline models1 have been already released.


Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Anil Kumar Uppugunduru ◽  
Syed Ershad Ahmed

Purpose Multipliers that form the basic building blocks in most of the error-resilient media processing applications are computationally intensive and power-hungry modules. Therefore, improving the multiplier’s performance in terms of area, critical path delay and power has become an important research area. This paper aims to propose two improved multiplier designs based on a new approximate compressor circuit to reduce the hardware complexity at the partial product reduction stage. The proposed approximate 4:2 compressor design significantly reduces the overall hardware cost of the multiplier. The error introduced by the approximate compressor is reduced using a new technique of assigning inputs to the compressors in the partial product reduction structure. Design/methodology/approach The multiplier designs implemented using the proposed approximate 4:2 compressor are targeted for error-resilient applications. For fair comparisons, various multiplier designs, including the proposed one, are implemented in MATLAB. The quality analysis is carried out using standard images, and metrics such as structural similarity index are computed to quantify the result of proposed designs with the existing architectures. Next, Verilog gate-level designs are synthesized to compute area, delay and power to prove the efficacy of the proposed designs. Findings Exhaustive error and hardware analysis have been carried out for the existing and proposed multiplier architectures. Error analysis carried out using MATLAB proves that the proposed designs achieve better quality metrics than existing designs. Hardware results show that area, the power consumed and critical path delay are reduced up to 39.8%, 51.7% and 15.9%, respectively, compared to the existing designs. Toward the end, the proposed designs impact is quantified and compared with existing designs on real-time image sharpening and image multiplication applications. Originality/value The area, delay and power metrics of the multiplier can be improved using an approximate compressor in an error-resilient application. Accordingly, in this work, a new compressor is proposed that reduces the hardware complexity in the multiplier architecture. However, the proposed approximate compressor, while reducing the computational complexity, tends to introduce error in the multiplier. The error introduced by the approximate compressor is reduced using a new technique of assigning inputs to the compressors in the partial product reduction structure. With the help of the approximate compressor and a technique of input realignment, hardware efficient and highly accurate multiplier designs are achieved.


Author(s):  
Julien Coche ◽  
Guillermo Romera Rodriguez ◽  
Aurélie Montarnal ◽  
Andrea Tapia ◽  
Frederick Benaben

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