Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)
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A new method for on-line state machine observation for embedded microprocessors

Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786) ◽

10.1109/hldvt.2000.889556 ◽

2002 ◽

Cited By ~ 4

Author(s):

M. Pflanz ◽

C. Galke ◽

H.T. Vierhaus

Keyword(s):

State Machine ◽

New Method ◽

On Line

Checking temporal properties under simulation of executable system descriptions

Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786) ◽

10.1109/hldvt.2000.889578 ◽

2002 ◽

Cited By ~ 4

Author(s):

J. Ruf ◽

D.W. Hoffmann ◽

T. Kropf ◽

W. Rosenstiel

Keyword(s):

Temporal Properties

Code simulation concept for S/390 processors using an emulation system

Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786) ◽

10.1109/hldvt.2000.889568 ◽

2002 ◽

Author(s):

S. Koerner

An RT-level fault model with high gate level correlation

Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786) ◽

10.1109/hldvt.2000.889551 ◽

2002 ◽

Cited By ~ 17

Author(s):

F. Corno ◽

G. Cumani ◽

M. Sonza Reorda ◽

G. Squillero

Keyword(s):

Fault Model

An approach to high-level synthesis system validation using formally verified transformations

Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786) ◽

10.1109/hldvt.2000.889564 ◽

2002 ◽

Cited By ~ 6

Author(s):

R. Radhakrishnan ◽

E. Teica ◽

R. Vermuri

Keyword(s):

High Level Synthesis ◽

Synthesis System ◽

System Validation ◽

High Level

Hardware/software co-debugging for reconfigurable computing

Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786) ◽

10.1109/hldvt.2000.889560 ◽

2002 ◽

Cited By ~ 6

Author(s):

K.A. Tomko ◽

A. Tiwari

Keyword(s):

Reconfigurable Computing

Silicon debug of a co-processor array for video applications

Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786) ◽

10.1109/hldvt.2000.889558 ◽

2002 ◽

Cited By ~ 9

Author(s):

B. Vermeulen ◽

G.J. van Rootselaar

Keyword(s):

Processor Array ◽

Silicon Debug

Use of constraint solving in order to generate test vectors for behavioral validation

Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786) ◽

10.1109/hldvt.2000.889553 ◽

2002 ◽

Cited By ~ 11

Author(s):

C. Pauli ◽

M.L. Nivet ◽

J.F. Santucci

Keyword(s):

Constraint Solving ◽

Test Vectors ◽

Behavioral Validation

Abstraction techniques for verification of multiple tightly coupled counters, registers and comparators

Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786) ◽

10.1109/hldvt.2000.889574 ◽

2002 ◽

Author(s):

Yee-Wing Hsieh ◽

S.P. Levitan

Keyword(s):

Tightly Coupled

A novel methodology for hierarchical test generation using functional constraint composition

Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786) ◽

10.1109/hldvt.2000.889552 ◽

2002 ◽

Cited By ~ 9

Author(s):

V.M. Vedula ◽

J.A. Abraham

Keyword(s):

Test Generation ◽

Functional Constraint

Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

A new method for on-line state machine observation for embedded microprocessors

Checking temporal properties under simulation of executable system descriptions

Code simulation concept for S/390 processors using an emulation system

An RT-level fault model with high gate level correlation

An approach to high-level synthesis system validation using formally verified transformations

Hardware/software co-debugging for reconfigurable computing

Silicon debug of a co-processor array for video applications

Use of constraint solving in order to generate test vectors for behavioral validation

Abstraction techniques for verification of multiple tightly coupled counters, registers and comparators

A novel methodology for hierarchical test generation using functional constraint composition

Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)
Latest Publications