Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)
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Published By IEEE Comput. Soc

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Test hardware design challenges in RF testing

Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) ◽

10.1109/vts.2002.1011130 ◽

2005 ◽

Author(s):

M. Slamani ◽

H. Ding

Keyword(s):

Hardware Design ◽

Rf Testing ◽

Design Challenges

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Innovations in test automation

Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) ◽

10.1109/vts.2002.1011109 ◽

2005 ◽

Author(s):

J. Sproch ◽

M. Howells ◽

J. Rajski

Keyword(s):

Test Automation

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Multi-gigahertz testing challenges and solutions

Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) ◽

10.1109/vts.2002.1011149 ◽

2005 ◽

Cited By ~ 1

Author(s):

K. Arabi ◽

K.-D. Hilliges ◽

D. Keezer ◽

S. Tabatabaei

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Analog and mixed signal BIST: too much, too little, too late?

Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) ◽

10.1109/vts.2002.1011134 ◽

2005 ◽

Cited By ~ 1

Author(s):

W. DeWilkins ◽

B. Baril ◽

A. Osseiran ◽

F. Muradali ◽

S. Tabatabaei ◽

...

Keyword(s):

Mixed Signal

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Validation and test of network processors and ASICs

Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) ◽

10.1109/vts.2002.1011172 ◽

2005 ◽

Author(s):

F. Karim ◽

H. Konuk ◽

Keesup Kim ◽

S. Dey

Keyword(s):

Network Processors

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SoCs with MEMS ? Can we include MEMS in the SoCs design and test flow ?

Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) ◽

10.1109/vts.2002.1011179 ◽

2005 ◽

Cited By ~ 6

Author(s):

S. Mir ◽

H. Kerkhoff ◽

R.D. Blanton ◽

H. Bederr ◽

H. Klim

Keyword(s):

Test Flow

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A successful DFT tester: what will it look like? is revolution in test approaches required?

Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) ◽

10.1109/vts.2002.1011116 ◽

2005 ◽

Author(s):

Lee Song ◽

R. Garcia ◽

A. Levy ◽

D. Wheater

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Programmable embedded IF source for wireless test

Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) ◽

10.1109/vts.2002.1011131 ◽

2005 ◽

Author(s):

W.R. Eisenstadt ◽

Sanghoon Choi

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A successful DFT tester: what will it look like? Is DFT tester a logical next step in ATE evolution?

Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) ◽

10.1109/vts.2002.1011123 ◽

2005 ◽

Author(s):

Lee Song ◽

P. Patton ◽

W. Radermacher

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Test as a key enabler for faster yield ramp-up

Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) ◽

10.1109/vts.2002.1011135 ◽

2005 ◽

Author(s):

J. Segal ◽

R. Segers

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Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc

Test hardware design challenges in RF testing

Innovations in test automation

Multi-gigahertz testing challenges and solutions

Analog and mixed signal BIST: too much, too little, too late?

Validation and test of network processors and ASICs

SoCs with MEMS ? Can we include MEMS in the SoCs design and test flow ?

A successful DFT tester: what will it look like? is revolution in test approaches required?

Programmable embedded IF source for wireless test

A successful DFT tester: what will it look like? Is DFT tester a logical next step in ATE evolution?

Test as a key enabler for faster yield ramp-up

Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)
Latest Publications