Plantar pressure measurement system based on piezoelectric sensor: a review

Purpose Plantar force is the interface pressure existing between the foot plantar surface and the shoe sole during static or dynamic gait. Plantar force derived from gait and posture plays a critical role for rehabilitation, footwear design, clinical diagnostics and sports activities, and so on. This paper aims to review plantar force measurement technologies based on piezoelectric materials, which can make the reader understand preliminary works systematically and provide convenience for researchers to further study. Design/methodology/approach The review introduces working principle of piezoelectric sensor, structures and hardware design of plantar force measurement systems based on piezoelectric materials. The structures of sensors in plantar force measurement systems can be divided into four kinds, including monolayered sensor, multilayered sensor, tri-axial sensor and other sensor. The previous studies about plantar force measurement system based on piezoelectric technology are reviewed in detail, and their characteristics and performances are compared. Findings A good deal of measurement technologies have been studied by researchers to detect and analyze the plantar force. Among these measurement technologies, taking advantage of easy fabrication and high sensitivity, piezoelectric sensor is an ideal candidate sensing element. However, the number and arrangement of the sensors will influence the characteristics and performances of plantar force measurement systems. Therefore, it is necessary to further study plantar force measurement system for better performances. Originality/value So far, many plantar force measurement systems have been proposed, and several reviews already introduced plantar force measurement systems in the aspect of types of pressure sensors, experimental setups for foot pressure measurement analysis and the technologies used in plantar shear stress measurements. However, this paper reviews plantar force measurement systems based on piezoelectric materials. The structures of piezoelectric sensors in the measurement systems are discussed. Hardware design applied to measurement system is summarized. Moreover, the main point of further study is presented in this paper.

The Right to Repair

In recent decades, companies around the world have deployed an arsenal of tools-including IP law, hardware design, software restrictions, pricing strategies, and marketing messages-to prevent consumers from fixing the things they own. While this strategy has enriched companies almost beyond measure, it has taken billions of dollars out of the pockets of consumers and imposed massive environmental costs on the planet. In The Right to Repair, Aaron Perzanowski analyzes the history of repair to show how we've arrived at this moment, when a battle over repair is being waged-largely unnoticed-in courtrooms, legislatures, and administrative agencies. With deft, lucid prose, Perzanowski explains the opaque and complex legal landscape that surrounds the right to repair and shows readers how to fight back.

Research on the Construction of an e-Commerce Marketing System Based on the Wireless Sensor Network

This paper takes e-commerce as the research object, based on the combination of wireless sensor network research results, using relevant theoretical analysis tools to identify several major problems in the marketing of enterprises. Then, the internal environment conditions of developing e-commerce are comprehensively analyzed through human resources, financial resources, marketing ability, and platform building ability, and the advantages and disadvantages of the enterprise itself are presented in a three-dimensional manner to help the enterprise understand its situation. Firstly, the overall hardware structure design of this paper is analyzed, and the network marketing node hardware design is proposed as the core of the system hardware design, and the marketing node hardware design circuit diagram is given through the selection of marketing node sensors, the selection of wireless communication modules, and the selection of marketing node microprocessors. Based on the specific application of the wireless sensor network in the e-commerce marketing system, the number of cluster selection is reduced by calculating and setting the remaining energy threshold of the cluster head for the whole network. The optimal cluster head is searched for based on the density of marketing nodes in different regions and the minimum energy consumption of the cluster after the division of the region within the cluster, and the original cluster head is replaced; the density of marketing nodes in different e-commerce is different, and the optimal number of cluster heads is searched for based on the minimum energy consumption of the network. In summary, three strategies are implemented to improve the design of wireless sensor network routing, and the effectiveness of the algorithm is verified through experimental simulation. Through the analysis of e-commerce operation, the intracluster congestion control is achieved by a dual-cluster head strategy with intracluster push selection of subcluster heads; the network nonuniform hierarchy and resource scheduling strategy achieve intercluster congestion mitigation and decongestion. A minimum energy consumption multihop path tree is also proposed here, which can achieve the lowest energy consumption of marketing nodes and networks and improve the link quality relative to other transmission paths. After simulation experiments, the effectiveness and reliability of the congestion algorithm are verified. A guarantee scheme is provided for the development of e-commerce marketing strategies to help breakthroughs and developments in marketing management, and an attempt is also made to provide a template for other enterprises to follow.

CFNTT: Scalable Radix-2/4 NTT Multiplication Architecture with an Efficient Conflict-free Memory Mapping Scheme

Number theoretic transform (NTT) is widely utilized to speed up polynomial multiplication, which is the critical computation bottleneck in a lot of cryptographic algorithms like lattice-based post-quantum cryptography (PQC) and homomorphic encryption (HE). One of the tendency for NTT hardware architecture is to support diverse security parameters and meet resource constraints on different computing platforms. Thus flexibility and Area-Time Product (ATP) become two crucial metrics in NTT hardware design. The flexibility of NTT in terms of different vector sizes and moduli can be obtained directly. Whereas the varying strides in memory access of in-place NTT render the design for different radix and number of parallel butterfly units a tough problem. This paper proposes an efficient conflict-free memory mapping scheme that supports the configuration for both multiple parallel butterfly units and arbitrary radix of NTT. Compared to other approaches, this scheme owns broader applicability and facilitates the parallelization of non-radix-2 NTT hardware design. Based on this scheme, we propose a scalable radix-2 and radix-4 NTT multiplication architecture by algorithm-hardware co-design. A dedicated schedule method is leveraged to reduce the number of modular additions/subtractions and modular multiplications in radix-4 butterfly unit by 20% and 33%, respectively. To avoid the bit-reversed cost and save memory footprint in arbitrary radix NTT/INTT, we put forward a general method by rearranging the loop structure and reusing the twiddle factors. The hardware-level optimization is achieved by excavating the symmetric operators in radix-4 butterfly unit, which saves almost 50% hardware resources compared to a straightforward implementation. Through experimental results and theoretical analysis, we point out that the radix-4 NTT with the same number of parallel butterfly units outperforms the radix-2 NTT in terms of area-time performance in the interleaved memory system. This advantage is enlarged when increasing the number of parallel butterfly units. For example, when processing 1024 14-bit points NTT with 8 parallel butterfly units, the ATP of LUT/FF/DSP/BRAM n radix-4 NTT core is approximately 2.2 × /1.2 × /1.1 × /1.9 × less than that of the radix-2 NTT core on a similar FPGA platform.