ASIC/SoC Functional Design Verification
Latest Publications

TOTAL DOCUMENTS

18

(FIVE YEARS 0)

H-INDEX

1

(FIVE YEARS 0)

Published By Springer International Publishing

9783319594170, 9783319594187

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Clock Domain Crossing (CDC) Verification

ASIC/SoC Functional Design Verification ◽

10.1007/978-3-319-59418-7_8 ◽

2017 ◽

pp. 149-166

Author(s):

Ashok B. Mehta

Introduction

ASIC/SoC Functional Design Verification ◽

10.1007/978-3-319-59418-7_1 ◽

2017 ◽

pp. 1-4

Author(s):

Ashok B. Mehta

Constrained Random Verification (CRV)

ASIC/SoC Functional Design Verification ◽

10.1007/978-3-319-59418-7_5 ◽

2017 ◽

pp. 65-74 ◽

Cited By ~ 1

Author(s):

Ashok B. Mehta

Keyword(s):

Constrained Random Verification

Analog/Mixed Signal (AMS) Verification

ASIC/SoC Functional Design Verification ◽

10.1007/978-3-319-59418-7_13 ◽

2017 ◽

pp. 255-271

Author(s):

Ashok B. Mehta

Keyword(s):

Mixed Signal

Functional Verification: Challenges and Solutions

ASIC/SoC Functional Design Verification ◽

10.1007/978-3-319-59418-7_2 ◽

2017 ◽

pp. 5-12

Author(s):

Ashok B. Mehta

Keyword(s):

Functional Verification

Cache Memory Subsystem Verification: UVM Agent Based

ASIC/SoC Functional Design Verification ◽

10.1007/978-3-319-59418-7_17 ◽

2017 ◽

pp. 311-318

Author(s):

Ashok B. Mehta

Keyword(s):

Cache Memory ◽

Agent Based ◽

Memory Subsystem

The Complete Product Design Life Cycle

ASIC/SoC Functional Design Verification ◽

10.1007/978-3-319-59418-7_15 ◽

2017 ◽

pp. 285-300

Author(s):

Ashok B. Mehta

Keyword(s):

Life Cycle ◽

Product Design ◽

Design Life ◽

Complete Product

SoC Interconnect Verification

ASIC/SoC Functional Design Verification ◽

10.1007/978-3-319-59418-7_14 ◽

2017 ◽

pp. 273-284

Author(s):

Ashok B. Mehta

Voice Over IP (VoIP) Network SoC Verification

ASIC/SoC Functional Design Verification ◽

10.1007/978-3-319-59418-7_16 ◽

2017 ◽

pp. 301-309

Author(s):

Ashok B. Mehta

Keyword(s):

Voice Over Ip

SystemVerilog Paradigm

ASIC/SoC Functional Design Verification ◽

10.1007/978-3-319-59418-7_3 ◽

2017 ◽

pp. 13-15

Author(s):

Ashok B. Mehta