Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition

2002 ◽

Cited By ~ 10

Author(s):

T. Riesgo ◽

J. Uceda

Keyword(s):

Fault Model ◽

Register Transfer Level ◽

Register Transfer

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A new concept for accurate modeling of VLSI interconnections and its application for timing simulation

Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition ◽

10.1109/eurdac.1996.558186 ◽

2002 ◽

Author(s):

B. Wunder ◽

G. Lehmann ◽

K.D. Muller-Glaser

Keyword(s):

Timing Simulation

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An integrated concept for design project planning and design flow control

Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition ◽

10.1109/eurdac.1996.558190 ◽

2002 ◽

Author(s):

M. Ryba ◽

U.G. Baitinger

Keyword(s):

Flow Control ◽

Project Planning ◽

Design Flow ◽

Design Project ◽

Planning And Design ◽

Integrated Concept

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System design using an integrated specification and performance modeling methodology

Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition ◽

10.1109/eurdac.1996.558256 ◽

2002 ◽

Author(s):

A. Sarkar

Keyword(s):

System Design ◽

Performance Modeling ◽

Modeling Methodology ◽

And Performance

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MORE: an alternative implementation of BDD packages by multi-operand synthesis

Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition ◽

10.1109/eurdac.1996.558200 ◽

2002 ◽

Cited By ~ 14

Author(s):

A. Hett ◽

R. Drechsler ◽

B. Becker

Download Full-text

Modeling ASIC memories in VHDL

Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition ◽

10.1109/eurdac.1996.558250 ◽

2002 ◽

Cited By ~ 2

Author(s):

E. Balaji ◽

P. Krishnamurthy

Download Full-text

Controller optimization for protocol intensive applications

Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition ◽

10.1109/eurdac.1996.558196 ◽

2002 ◽

Cited By ~ 6

Author(s):

A. Crews ◽

F. Brewer

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A hierarchical approach to the analog behavioral modeling of neural networks using HDL-A

Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition ◽

10.1109/eurdac.1996.558015 ◽

2002 ◽

Cited By ~ 1

Author(s):

M.M. Ahmed ◽

H.F. Ragaie ◽

H. Haddara

Keyword(s):

Neural Networks ◽

Behavioral Modeling ◽

Hierarchical Approach

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A heuristic covering technique for optimizing average-case delay in the technology mapping of asynchronous burst-mode circuits

Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition ◽

10.1109/eurdac.1996.558218 ◽

2002 ◽

Cited By ~ 2

Author(s):

P.A. Beerel ◽

K.Y. Yun ◽

Wei-Chun Chou

Keyword(s):

Technology Mapping ◽

Average Case ◽

Burst Mode ◽

Covering Technique

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Beyond VHDL: textual formalisms, visual techniques, or both?

Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition ◽

10.1109/eurdac.1996.558238 ◽

2002 ◽

Author(s):

F.J. Rammig

Download Full-text

Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc. Press

A fault model for VHDL descriptions at the register transfer level

A new concept for accurate modeling of VLSI interconnections and its application for timing simulation

An integrated concept for design project planning and design flow control

System design using an integrated specification and performance modeling methodology

MORE: an alternative implementation of BDD packages by multi-operand synthesis

Modeling ASIC memories in VHDL

Controller optimization for protocol intensive applications

A hierarchical approach to the analog behavioral modeling of neural networks using HDL-A

A heuristic covering technique for optimizing average-case delay in the technology mapping of asynchronous burst-mode circuits

Beyond VHDL: textual formalisms, visual techniques, or both?

Export Citation Format

Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and ExhibitionLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc. Press

A fault model for VHDL descriptions at the register transfer level

A new concept for accurate modeling of VLSI interconnections and its application for timing simulation

An integrated concept for design project planning and design flow control

System design using an integrated specification and performance modeling methodology

MORE: an alternative implementation of BDD packages by multi-operand synthesis

Modeling ASIC memories in VHDL

Controller optimization for protocol intensive applications

A hierarchical approach to the analog behavioral modeling of neural networks using HDL-A

A heuristic covering technique for optimizing average-case delay in the technology mapping of asynchronous burst-mode circuits

Beyond VHDL: textual formalisms, visual techniques, or both?

Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition
Latest Publications