Embedded linear model predictive control in field-programmable gate array using register-transfer level implementation and floating-point representation applied to a quadrotor system model

Model predictive control is increasingly becoming a popular control strategy for a wide range of applications in both industry and academia, mainly motivated by its ability to systematically handle constraints imposed on a system, regardless of its nature. However, this generates high computational demands, limiting the applicability of model predictive control. Field-programmable gate arrays are reconfigurable hardware platforms that allow the parallel implementation of model predictive control, accelerating such algorithms, but most works found in the literature opt to use high-level synthesis tools and fixed-point numeric representation to generate embedded controllers, resulting in faster-designed solutions but not exactly efficient and flexible ones, that can be applied to different scenarios. Regarding such matter, this work proposes the manual implementation (register-transfer level implementation) of linear model predictive control and the usage of floating-point numeric representation applied to a quadrotor system. The initial results obtained using the proposed controller are presented in this article, achieving 29.34 ms of calculation time at 50 MHz for the attitude control of a quadrotor model containing twelve states and four control outputs.

Bridging the Gap between RTL and Software Fault Injection

Protecting programs against hardware fault injection requires accurate software fault models. However, typical models, such as the instruction skip, do not take into account the microarchitecture specificities of a processor. We propose in this article an approach to study the relation between faults at the Register Transfer Level (RTL) and faults at the software level. The goal is twofold: accurately model RTL faults at the software level and materialize software fault models to actual RTL injections. These goals lead to a better understanding of a system's security against hardware fault injection, which is important to design effective and cost-efficient countermeasures. Our approach is based on the comparison between results from RTL simulations and software injections (using a program mutation tool). Various analyses are included in this article to give insight on the relevance of software fault models, such as the computation of a coverage and fidelity metric, and to link software fault models to hardware RTL descriptions. These analyses are applied on various single-bit and multiple-bit injection campaigns to study the faulty behaviors of a RISC-V processor.