2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)

Reconfiguration in FPGA-based multi-core platforms for hard real-time applications

2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) ◽

10.1109/recosoc.2016.7533895 ◽

2016 ◽

Cited By ~ 4

Author(s):

Luca Pezzarossa ◽

Martin Schoeberl ◽

Jens Sparso

Keyword(s):

Real Time ◽

Real Time Applications ◽

Hard Real Time

Efficient bandwidth regulation at memory controller for mixed criticality applications

2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) ◽

10.1109/recosoc.2016.7533902 ◽

2016 ◽

Cited By ~ 1

Author(s):

George Tsamis ◽

Stamatis Kavvadias ◽

Antonis Papagrigoriou ◽

Miltos D. Grammatikakis ◽

Kyprianos Papadimitriou

Keyword(s):

Memory Controller ◽

Mixed Criticality

ERRCA: A buffer-efficient reconfigurable optical Network-on-Chip with permanent-error recognition

2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) ◽

10.1109/recosoc.2016.7533909 ◽

2016 ◽

Author(s):

Wolfgang Buter ◽

Dominic Oehlert ◽

A. Garcia-Ortiz

Keyword(s):

Optical Network ◽

Network On Chip ◽

Error Recognition ◽

On Chip

A programming model for reconfigurable computing based in functional concurrency

2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) ◽

10.1109/recosoc.2016.7533911 ◽

2016 ◽

Cited By ~ 1

Author(s):

William L. Harrison ◽

Ian Graves ◽

Adam Procter ◽

Michela Becchi ◽

Gerard Allwein

Keyword(s):

Reconfigurable Computing ◽

Programming Model

An ultra-low energy PUF matching security platform using programmable delay lines

2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) ◽

10.1109/recosoc.2016.7533899 ◽

2016 ◽

Cited By ~ 2

Author(s):

Teng Xu ◽

Hongxiang Gu ◽

Miodrag Potkonjak

Keyword(s):

Low Energy ◽

Delay Lines

A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip

2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) ◽

10.1109/recosoc.2016.7533908 ◽

2016 ◽

Cited By ~ 3

Author(s):

Jan Moritz Joseph ◽

Sven Wrieden ◽

Christopher Blochwitz ◽

Alberto Garcia-Oritz ◽

Thilo Pionteck

Keyword(s):

Design Space Exploration ◽

Design Space ◽

Space Exploration ◽

Network On Chip ◽

Simulation Environment ◽

3D Network ◽

On Chip

Verifying worst-case completion times for reconfigurable hardware modules using proof-carrying hardware

2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) ◽

10.1109/recosoc.2016.7533910 ◽

2016 ◽

Cited By ~ 1

Author(s):

Tobias Wiersema ◽

Marco Platzner

Keyword(s):

Reconfigurable Hardware ◽

Worst Case ◽

Completion Times

Online reconfigurable routing method for handling link failures in NoC-based MPSoCs

2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) ◽

10.1109/recosoc.2016.7533905 ◽

2016 ◽

Author(s):

Poona Bahrebar ◽

Dirk Stroobandt

Keyword(s):

Link Failures ◽

Routing Method

The selector-tree network: A new self-routing and non-blocking interconnection network

2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) ◽

10.1109/recosoc.2016.7533894 ◽

2016 ◽

Cited By ~ 2

Author(s):

Tripti Jain ◽

Klaus Schneider ◽

Anoop Bhagyanath

Keyword(s):

Interconnection Network ◽

Tree Network

2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Reconfiguration in FPGA-based multi-core platforms for hard real-time applications

Efficient bandwidth regulation at memory controller for mixed criticality applications

ERRCA: A buffer-efficient reconfigurable optical Network-on-Chip with permanent-error recognition

A programming model for reconfigurable computing based in functional concurrency

An ultra-low energy PUF matching security platform using programmable delay lines

A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip

Verifying worst-case completion times for reconfigurable hardware modules using proof-carrying hardware

Table of contents

Online reconfigurable routing method for handling link failures in NoC-based MPSoCs

The selector-tree network: A new self-routing and non-blocking interconnection network

Export Citation Format

2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Reconfiguration in FPGA-based multi-core platforms for hard real-time applications

Efficient bandwidth regulation at memory controller for mixed criticality applications

ERRCA: A buffer-efficient reconfigurable optical Network-on-Chip with permanent-error recognition

A programming model for reconfigurable computing based in functional concurrency

An ultra-low energy PUF matching security platform using programmable delay lines

A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip

Verifying worst-case completion times for reconfigurable hardware modules using proof-carrying hardware

Table of contents

Online reconfigurable routing method for handling link failures in NoC-based MPSoCs

The selector-tree network: A new self-routing and non-blocking interconnection network

2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
Latest Publications