Extended dissipative-based state estimation for Markov jump coupled neural networks with reaction-diffusion terms

This work mainly concentrates on the state estimation for Markov jump coupled neural networks (MJCNNs) with reaction-diffusion terms, in which the memory controller is employed. First, the considered MJCNNs model is introduced, and the dynamic error system can be obtained based on the proposed state estimator. Then, a memory controller that involves constant signal transmission delay is designed. Moreover, by Lyapunov functional method, inequality technique and Kronecker product law, a novel stable and extended dissipative analysis criteria can be established to ensure that the stability of the error system the error system. Meanwhile, the controller gains can be obtained by solving linear matrix inequalities. Finally, a numerical example is given to illustrate the effectiveness of the developed method.

The design of a memory controller for DDR SDRAM

Memory system performance is an important factor in determining overall system performance. The design of key components of the memory system, such as the memory controller, becomes more important as memory performance becomes a limiting factor in high performance computing. This work focuses on the design of a unit which sends control signals to Double Data Rate Synchronous Dram (DDR SDRAM). The design is based on established concepts such as access reordering. A novel, adaptive page policy based on a machine learning algorithm has been developed in this work and evaluated with traditional page policies. the work illustrates some of the design trade-offs in a memory controller and the performance of the designs when using real application address traces.The results show that access reordering improves the performance of DDR SDRAM compared to in-order scheduling (up to 50% improvement) and that scheduling multiple requests can result in latency hiding. The dynamic page policy approximates the best static page policy in most cases.

The design of a memory controller for DDR SDRAM

Memory system performance is an important factor in determining overall system performance. The design of key components of the memory system, such as the memory controller, becomes more important as memory performance becomes a limiting factor in high performance computing. This work focuses on the design of a unit which sends control signals to Double Data Rate Synchronous Dram (DDR SDRAM). The design is based on established concepts such as access reordering. A novel, adaptive page policy based on a machine learning algorithm has been developed in this work and evaluated with traditional page policies. the work illustrates some of the design trade-offs in a memory controller and the performance of the designs when using real application address traces.The results show that access reordering improves the performance of DDR SDRAM compared to in-order scheduling (up to 50% improvement) and that scheduling multiple requests can result in latency hiding. The dynamic page policy approximates the best static page policy in most cases.

Memory Access Optimization of a Neural Network Accelerator Based on Memory Controller

Special accelerator architecture has achieved great success in processor architecture, and it is trending in computer architecture development. However, as the memory access pattern of an accelerator is relatively complicated, the memory access performance is relatively poor, limiting the overall performance improvement of hardware accelerators. Moreover, memory controllers for hardware accelerators have been scarcely researched. We consider that a special accelerator memory controller is essential for improving the memory access performance. To this end, we propose a dynamic random access memory (DRAM) memory controller called NNAMC for neural network accelerators, which monitors the memory access stream of an accelerator and transfers it to the optimal address mapping scheme bank based on the memory access characteristics. NNAMC includes a stream access prediction unit (SAPU) that analyzes the type of data stream accessed by the accelerator via hardware, and designs the address mapping for different banks using a bank partitioning model (BPM). The image mapping method and hardware architecture were analyzed in a practical neural network accelerator. In the experiment, NNAMC achieved significantly lower access latency of the hardware accelerator than the competing address mapping schemes, increased the row buffer hit ratio by 13.68% on average (up to 26.17%), reduced the system access latency by 26.3% on average (up to 37.68%), and lowered the hardware cost. In addition, we also confirmed that NNAMC efficiently adapted to different network parameters.

Memory-Based Semantic Parsing

We present a memory-based model for context- dependent semantic parsing. Previous approaches focus on enabling the decoder to copy or modify the parse from the previous utterance, assuming there is a dependency between the current and previous parses. In this work, we propose to represent contextual information using an external memory. We learn a context memory controller that manages the memory by maintaining the cumulative meaning of sequential user utterances. We evaluate our approach on three semantic parsing benchmarks. Experimental results show that our model can better process context-dependent information and demonstrates improved performance without using task-specific decoders.