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2018 IEEE 36th VLSI Test Symposium (VTS)
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TOTAL DOCUMENTS
58
(FIVE YEARS 0)
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6
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Published By IEEE
9781538637746
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Innovative practices on design & test for flexible hybrid electronics
2018 IEEE 36th VLSI Test Symposium (VTS)
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10.1109/vts.2018.8368668
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2018
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Author(s):
Tsung-Ching Jim Huang
◽
Jason Marsh
◽
Scott H. Goodwin
◽
Dorota S. Temple
◽
Tsung-Ching Jim Huang
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Hardware Trojan attacks in embedded memory
2018 IEEE 36th VLSI Test Symposium (VTS)
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10.1109/vts.2018.8368630
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2018
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Cited By ~ 10
Author(s):
Tamzidul Hoque
◽
Xinmu Wang
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Abhishek Basak
◽
Robert Karam
◽
Swarup Bhunia
Keyword(s):
Hardware Trojan
◽
Embedded Memory
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VTS 2018 organizing committee
2018 IEEE 36th VLSI Test Symposium (VTS)
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10.1109/vts.2018.8368616
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2018
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Systematic b-adjacent symbol error correcting reed-solomon codes with parallel decoding
2018 IEEE 36th VLSI Test Symposium (VTS)
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10.1109/vts.2018.8368650
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2018
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Cited By ~ 1
Author(s):
Abhishek Das
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Nur A. Touba
Keyword(s):
Reed Solomon Codes
◽
Parallel Decoding
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Test challenges and solutions for emerging non-volatile memories
2018 IEEE 36th VLSI Test Symposium (VTS)
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10.1109/vts.2018.8368632
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2018
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Author(s):
Mohammad Nasim Imtiaz Khan
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Swaroop Ghosh
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Special session on BIST/calibration of A/MS devices
2018 IEEE 36th VLSI Test Symposium (VTS)
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10.1109/vts.2018.8368653
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2018
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Author(s):
Hans-Mart von Staudt
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James Izon
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Sule Ozev
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Peter Sarson
Keyword(s):
Special Session
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[Copyright notice]
2018 IEEE 36th VLSI Test Symposium (VTS)
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10.1109/vts.2018.8368614
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2018
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Keyword(s):
Copyright Notice
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Innovative practices on functional testing and fault simulation for FuSa
2018 IEEE 36th VLSI Test Symposium (VTS)
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10.1109/vts.2018.8368639
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2018
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Author(s):
Anandh Krishnan
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John van Gelder
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Mayukh Bhattacharya
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Sreejit Chakravarty
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Prashant Goteti
Keyword(s):
Fault Simulation
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Functional Testing
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Exploiting built-in delay lines for applying launch-on-capture at-speed testing on self-timed circuits
2018 IEEE 36th VLSI Test Symposium (VTS)
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10.1109/vts.2018.8368637
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2018
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Cited By ~ 2
Author(s):
Omar Al-Terkawi Hasib
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Daniel Crepeau
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Thomas Awad
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Andrei Dulipovici
◽
Yvon Savaria
◽
...
Keyword(s):
Delay Lines
◽
Timed Circuits
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Innovative practices on test in Japan
2018 IEEE 36th VLSI Test Symposium (VTS)
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10.1109/vts.2018.8368644
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2018
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Author(s):
Koji Asami
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Yoshiro Tamura
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Haruo Kobayashi
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Jun Matsushima
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Yoichi Maeda
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...
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