Advances in Emerging Memory Technologies: From Data Storage to Artificial Intelligence

This paper presents an overview of emerging memory technologies. It begins with the presentation of stand-alone and embedded memory technology evolution, since the appearance of Flash memory in the 1980s. Then, the progress of emerging memory technologies (based on filamentary, phase change, magnetic, and ferroelectric mechanisms) is presented with a review of the major demonstrations in the literature. The potential of these technologies for storage applications addressing various markets and products is discussed. Finally, we discuss how the rise of artificial intelligence and bio-inspired circuits offers an opportunity for emerging memory technology and shifts the application from pure data storage to storage and computing tasks, and also enlarges the range of required specifications at the device level due to the exponential number of new systems and architectures.

Stability Analysis of Fractional Order Memristor Synapse-coupled Hopfield Neural Network with Ring Structure

A memristor is a non-linear two-terminal electrical element that incorporates memory features and nanoscale properties, enabling us to design very high-density artificial neural networks. To examine the embedded memory property, we should use mathematical frameworks like fractional calculus, which is capable of doing so. Here, we first present a fractional-order memristor synapse-coupling Hopfield neural network on two neurons and then extend the model to a neural network with a ring structure that consists of $n$ sub-network neurons. Necessary and sufficient conditions for the stability of equilibrium points are investigated, highlighting the dependency of the stability on the fractional-order value and the number of neurons. Numerical simulations and bifurcation analysis, along with Lyapunov exponents, are given in the two-neuron case that substantiates the theoretical findings, suggesting possible routes towards chaos when the fractional order of the system increases. In the $n$-neuron case also, it is revealed that the stability depends on the structure and number of sub-networks.

Embbedded System-on-Chip 3D Localization and Mapping—eSoC-SLAM

This paper discusses a novel embedded system-on-chip 3D localization and mapping (eSoC-LAM) implementation, that followed a co-design approach with the primary aim of being deployed in a small system on a programmable chip (SoPC), the Intel’s (a.k.a Altera) Cyclone V 5CSEMA5F31C6N, available in the Terasic’s board DE1-SoC. This computer board incorporates an 800 MHz Dual-core ARM Cortex-A9 and a Cyclone V FPGA with 85k programmable logic elements and 4450 Kbits of embedded memory running at 50 MHz. We report experiments of the eSoC-LAM implementation using a Robosense’s 3D LiDAR RS-16 sensor in a Robotis’ TurtleBot2 differential robot, both controlled by a Terasic’s board DE1-SoC. This paper presents a comprehensive description of the designed architecture, design constraints, resource optimization, HPS-FPGA exchange of information, and co-design results. The eSoC-LAM implementation reached an average speed-up of 6.5× when compared with a version of the algorithm running in a the hard processor system of the Cyclone V device, and a performance of nearly 32 fps, while keeping high map accuracy.

MBIST Controller Based on March-ee Algorithm

In the modern System on Chip (SoC)-based designs, embedded memory occupies the majority of the area. Therefore, the demand for fast self-testing plays a vital role in the SoC device as its memory density increases. The focus of this research study is to provide a self-testing mechanism integrated with the SoC design for fault diagnosis and failure analysis. In particular, this paper proposes a controller design to test memories at SoC devices, called a memory built-in self-test (MBIST) controller. This controller works on the principle of the proposed March-ee (enhanced elements) algorithm with the primary objective to improve the test speed, fault coverage, and power consumption at a low area overhead. The complete design of the MBIST controller with the associated March-ee algorithm is minimal and easy to be integrated into any SoC device to provide a vibrant feature of memory fault detection. The results obtained are compared with that provided by the existing March algorithms, using the same design specifications, where the proposed March-ee MBIST controller has shown better results in terms of power consumption, fault coverage, timing, and area.