2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC)
Latest Publications

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Published By IEEE

9781509035311

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Data and Commands Communication Protocol for Neuromorphic Platform Configuration

2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC) ◽

10.1109/mcsoc.2016.41 ◽

2016 ◽

Cited By ~ 2

Author(s):

Alessandro Siino ◽

Francesco Barchi ◽

Sergio Davies ◽

Gianvito Urgese ◽

Andrea Acquaviva

Keyword(s):

Communication Protocol

Accelerating Multicore Architecture Simulation Using Application Profile

2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC) ◽

10.1109/mcsoc.2016.16 ◽

2016 ◽

Author(s):

Keiji Kimura ◽

Gakuho Taguchi ◽

Hironori Kasahara

Keyword(s):

Multicore Architecture ◽

Application Profile ◽

Architecture Simulation

Acceleration of Full-PIC Simulation on a CPU-FPGA Tightly Coupled Environment

2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC) ◽

10.1109/mcsoc.2016.33 ◽

2016 ◽

Cited By ~ 4

Author(s):

Ryotaro Sakai ◽

Naru Sugimoto ◽

Takaaki Miyajima ◽

Naoyuki Fujita ◽

Hideharu Amano

Keyword(s):

Pic Simulation ◽

Tightly Coupled

A Data Locality and Memory Contention Analysis Method in Embedded NUMA Multi-core Systems

2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC) ◽

10.1109/mcsoc.2016.15 ◽

2016 ◽

Cited By ~ 1

Author(s):

Lin Li ◽

Markus Fussenegger ◽

Gordon Cichon

Keyword(s):

Data Locality ◽

Analysis Method ◽

Memory Contention

Distributed Dynamic Rate Adaptation on a Network on Chip with Traffic Distortion

2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC) ◽

10.1109/mcsoc.2016.29 ◽

2016 ◽

Cited By ~ 2

Author(s):

Yves Durand ◽

Christian Bernard ◽

Fabien Clermidy

Keyword(s):

Rate Adaptation ◽

Network On Chip ◽

On Chip

Improvement of Line Coding Overhead Targeting Both Run-Length and DC-Balance

2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC) ◽

10.1109/mcsoc.2016.45 ◽

2016 ◽

Author(s):

Sarat Yoowattana ◽

Tomohiro Yoneda

Keyword(s):

Run Length

Automatic Thread-Block Size Adjustment for Memory-Bound BLAS Kernels on GPUs

2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC) ◽

10.1109/mcsoc.2016.32 ◽

2016 ◽

Cited By ~ 2

Author(s):

Daichi Mukunoki ◽

Toshiyuki Imamura ◽

Daisuke Takahashi

Keyword(s):

Block Size ◽

Thread Block ◽

Size Adjustment

IEEE MCSoC-16 Organization

2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC) ◽

10.1109/mcsoc.2016.6 ◽

2016 ◽

High-Precision Power Modelling of the Tegra K1 Variable SMP Processor Architecture

2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC) ◽

10.1109/mcsoc.2016.28 ◽

2016 ◽

Cited By ~ 4

Author(s):

Kristoffer Robin Stokke ◽

Hakon Kvale Stensland ◽

Pal Halvorsen ◽

Carsten Griwodz

Keyword(s):

High Precision ◽

Processor Architecture

Communication-Based Power Modelling for Heterogeneous Multiprocessor Architectures

2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC) ◽

10.1109/mcsoc.2016.27 ◽

2016 ◽

Cited By ~ 1

Author(s):

Baptiste Roux ◽

Matthieu Gautier ◽

Olivier Sentieys ◽

Steven Derrien

Keyword(s):

Multiprocessor Architectures ◽

Heterogeneous Multiprocessor

2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Data and Commands Communication Protocol for Neuromorphic Platform Configuration

Accelerating Multicore Architecture Simulation Using Application Profile

Acceleration of Full-PIC Simulation on a CPU-FPGA Tightly Coupled Environment

A Data Locality and Memory Contention Analysis Method in Embedded NUMA Multi-core Systems

Distributed Dynamic Rate Adaptation on a Network on Chip with Traffic Distortion

Improvement of Line Coding Overhead Targeting Both Run-Length and DC-Balance

Automatic Thread-Block Size Adjustment for Memory-Bound BLAS Kernels on GPUs

IEEE MCSoC-16 Organization

High-Precision Power Modelling of the Tegra K1 Variable SMP Processor Architecture

Communication-Based Power Modelling for Heterogeneous Multiprocessor Architectures

2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC)
Latest Publications