Redesigning Vina@QNLM for Ultra-Large-Scale Molecular Docking and Screening on a Sunway Supercomputer

Ultra-large-scale molecular docking can improve the accuracy of lead compounds in drug discovery. In this study, we developed a molecular docking piece of software, Vina@QNLM, which can use more than 4,80,000 parallel processes to search for potential lead compounds from hundreds of millions of compounds. We proposed a task scheduling mechanism for large-scale parallelism based on Vinardo and Sunway supercomputer architecture. Then, we readopted the core docking algorithm to incorporate the full advantage of the heterogeneous multicore processor architecture in intensive computing. We successfully expanded it to 10, 465, 065 cores (1,61,001 management process elements and 0, 465, 065 computing process elements), with a strong scalability of 55.92%. To the best of our knowledge, this is the first time that 10 million cores are used for molecular docking on Sunway. The introduction of the heterogeneous multicore processor architecture achieved the best speedup, which is 11x more than that of the management process element of Sunway. The performance of Vina@QNLM was comprehensively evaluated using the CASF-2013 and CASF-2016 protein–ligand benchmarks, and the screening power was the highest out of the 27 pieces of software tested in the CASF-2013 benchmark. In some existing applications, we used Vina@QNLM to dock more than 10 million molecules to nine rigid proteins related to SARS-CoV-2 within 8.5 h on 10 million cores. We also developed a platform for the general public to use the software.

Design and Assertion Based Verification of RISC-V Processor Subsystems

RISC-V is an open, free standard architecture. As its open-source architecture, it can be used in multiple applications like embedded processors, IoT, artificial intelligence, machine learning, military and defense applications. The parameters like throughput, performance, high speed etc., become essential in designing processor architecture. Pipelining is one such unique feature supported by RISC-V ISA, which basically involves the execution of multiple instructions in single cycle. This feature helps in improving the performance of the processor architecture. RISC-V ISA supports five stages of pipelining they are instruction fetch, instruction decode, execute, memory and write-back stage. The work covered in this paper involves the design and implementation of the subsystems of the RISC-V ISA which are present in different stages of pipeline architecture. The subsystems included in this work are Floating Point Unit (FPU) of Execute stage, Branch Prediction Unit (BPU) of instruction fetch stage, Forwarding Unit of execution stage, Operand Logic of decode stage and Floating-Point register file of Write-back stage. These subsystems are designed using Verilog Hardware Description Language in Xilinx ISE. Followed by the implementation the verification of the floating-point unit and the forwarding unit is performed using System Verilog Assertions in QuestaSim. The Assertion coverage report for the same is extracted.

Vectorizing posit operations on RISC-V for faster deep neural networks: experiments and comparison with ARM SVE

With the arrival of the open-source RISC-V processor architecture, there is the chance to rethink Deep Neural Networks (DNNs) and information representation and processing. In this work, we will exploit the following ideas: i) reduce the number of bits needed to represent the weights of the DNNs using our recent findings and implementation of the posit number system, ii) exploit RISC-V vectorization as much as possible to speed up the format encoding/decoding, the evaluation of activations functions (using only arithmetic and logic operations, exploiting approximated formulas) and the computation of core DNNs matrix-vector operations. The comparison with the well-established architecture ARM Scalable Vector Extension is natural and challenging due to its closedness and mature nature. The results show how it is possible to vectorize posit operations on RISC-V, gaining a substantial speed-up on all the operations involved. Furthermore, the experimental outcomes highlight how the new architecture can catch up, in terms of performance, with the more mature ARM architecture. Towards this end, the present study is important because it anticipates the results that we expect to achieve when we will have an open RISC-V hardware co-processor capable to operate natively with posits.

Realization of advantages of Russian processor architecture KOMDIV64 in technical means of complexes of civil purpose automation

The paper discusses the practical issues of creation cluster-type computing equipment and switching equipment, which are based on Russian technologies and components developed for the segment of high-performance teraflop-class servers. A number of technical solutions are proposed, aimed at forming in the shortest possible time with minimal costs using a limited set of components (clusters), a model range of cluster-type computing equipment. The latter should ensure the creation of technical means of automation systems that have a performance parity with technical means of foreign production, as well as surpass it in a number of important operational and technical parameters, including the duration of the products and technical means life cycle, failure stability and external influencing factors durability.