Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
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Published By IEEE Comput. Soc. Press

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Modeling of 3-dimensional defects in integrated circuits

Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dftvs.1992.224355 ◽

2003 ◽

Author(s):

J.P. de Gyvez ◽

S.M. Dani

Keyword(s):

Integrated Circuits ◽

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On fault probabilities and yield models for analog VLSI neural networks

Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dftvs.1992.224358 ◽

2003 ◽

Author(s):

P.M. Furth ◽

A.G. Andreou

Keyword(s):

Neural Networks ◽

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Improved layer assignment for packaging multichip modules

Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dftvs.1992.224343 ◽

2003 ◽

Author(s):

C.-H. Chen ◽

M.H. Heydari ◽

I.G. Tollis ◽

C. Xia

Keyword(s):

Multichip Modules ◽

Layer Assignment

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Nondeterministic adaptive routing techniques for WSI processor arrays

Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dftvs.1992.224357 ◽

2003 ◽

Author(s):

D.C. Blight ◽

R.D. McLeod

Keyword(s):

Adaptive Routing ◽

Processor Arrays ◽

Routing Techniques

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Application of yield models for semiconductor yield improvement

Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dftvs.1992.224349 ◽

2003 ◽

Author(s):

D.L. Dance ◽

R. Jarvis

Keyword(s):

Yield Improvement

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A fast pipelined complex multiplier: the fault tolerance issues

Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dftvs.1992.224347 ◽

2003 ◽

Author(s):

L. Breveglieri ◽

V. Piuri ◽

D. Sciuto

Keyword(s):

Fault Tolerance ◽

Complex Multiplier

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Recognition of catastrophic faults

Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dftvs.1992.224370 ◽

2003 ◽

Author(s):

A. Nayak ◽

L. Pagli ◽

N. Santoro

Keyword(s):

Catastrophic Faults

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Design rule centring for row redundant content addressable memories

Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dftvs.1992.224353 ◽

2003 ◽

Author(s):

W.B. Noghani ◽

I.P. Jalowiecki

Keyword(s):

Design Rule ◽

Content Addressable Memories

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Bridging faults modeling and detection in CMOS combinational gates

Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dftvs.1992.224371 ◽

2003 ◽

Author(s):

G. Buonanno ◽

D. Sciuto

Keyword(s):

Bridging Faults

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Defect level estimation for digital ICs

Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dftvs.1992.224363 ◽

2003 ◽

Author(s):

J.J.T. Sousa ◽

J.P. Teixeira

Keyword(s):

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