High-performance FPGA implementation of the secure hash algorithm 3 for single and multi-message processing

<span>The secure hash function has become the default choice for information security, especially in applications that require data storing or manipulation. Consequently, optimized implementations of these functions in terms of Throughput or Area are in high demand. In this work we propose a new conception of the secure hash algorithm 3 (SHA-3), which aim to increase the performance of this function by using pipelining, four types of pipelining are proposed two, three, four, and six pipelining stages. This approach allows us to design data paths of SHA-3 with higher Throughput and higher clock frequencies. The design reaches a maximum Throughput of 102.98 Gbps on Virtex 5 and 115.124 Gbps on Virtex 6 in the case of the 6 stages, for 512 bits output length. Although the utilization of the resource increase with the increase of the number of the cores used in each one of the cases. The proposed designs are coded in very high-speed integrated circuits program (VHSIC) hardware description language (VHDL) and implemented in Xilinx Virtex-5 and Virtex-6 A field-programmable gate array (FPGA) devices and compared to existing FPGA implementations.</span>

Review on Different Microcontroller Boards Used in IoT

Today’s technology has been evolved into stand-alone systems which can do all necessary processes by themselves without any additional hardware. Advance microcontrollers have become microcomputers that are also known as single board computers. These systems take their power from powerful microcontrollers. These microcontrollers have many integrated circuits on board so they can achieve many different processes by themselves. They are being used in many applications from powerful industrial devices to simple home appliances. In today’s market, there are many different microcontrollers with different structure and capabilities. Therefore, understanding the concepts related to the microcontrollers is really important for choosing the best hardware. This paper presents the main concepts of microcontrollers and reveals the basis of their structure. Their components and abilities have been discussed and a comparison of well-known single board computers has been given. Keywords: Microcontrollers, Integrated Circuits, Arduino UNO, Raspberry PI, BeagleBone Black, ESP8266.

Fault Injection Attack Emulation Framework for Early Evaluation of IC Designs

Fault injection attack (FIA) has become a serious threat to the confidentiality and fault tolerance of integrated circuits (ICs). Circuit designers need an effective method to evaluate the countermeasures of the IC designs against the FIAs at the design stage. To address the need, this article, based on FPGA emulation, proposes an in-circuit early evaluation framework, in which FIAs are emulated with parameterized fault models. To mimic FIAs, an efficient scan approach is proposed to inject faults at any time at any circuit nodes, while both the time and area overhead of fault injection are reduced. After the circuit design under test (CUT) is submitted to the framework, the scan chains insertion, fault generation, and fault injection are executed automatically, and the evaluation result of the CUT is generated, making the evaluation a transparent process to the designers. Based on the framework, the confidentiality and fault-tolerance evaluations are demonstrated with an information-based evaluation approach. Experiment results on a set of ISCAS89 benchmark circuits show that on average, our approach reduces the area overhead by 41.08% compared with the full scan approach and by over 20.00% compared with existing approaches. The confidentiality evaluation experiments on AES-128 and DES-56 and the fault-tolerance evaluation experiments on two CNN circuits, a RISC-V core, a Cordic core, and the float point arithmetic units show the effectiveness of the proposed framework.

A ReRAM Memory Compiler for Monolithic 3D Integrated Circuits in a Carbon Nanotube Process

We present a ReRAM memory compiler for monolithic 3D (M3D) integrated circuits (IC). We develop ReRAM architectures for M3D ICs using 1T-1R bit cells and single and multiple tiers of transistors for access and peripheral circuits. The compiler includes an automated flow for generation of subarrays of different dimensions and larger arrays of a target capacity by integrating multiple subarrays. The compiler is demonstrated using an M3D process design kit (PDK) based on a Carbon Nanotube Transistor technology. The PDK includes multiple layers of transistors and back-end-of-the-line integrated ReRAM. Simulations show the compiled ReRAM macros with multiple tiers of transistors reduces footprint and improves performance over the macros with single-tier transistors. The compiler creates layout views that are exported into library exchange format or graphic data system for full-array assembly and schematic/symbol views to extract per-bit read/write energy and read latency. Comparison of the proposed M3D subarray architectures with baseline 2D subarrays, generated with a custom-designed set of bit cells and peripherals, demonstrate up to 48% area reduction and 13% latency improvement.

Novel add-drop filter based on serial and parallel photonic crystal ring resonators (PCRR)

Photonic crystal ring resonators (PCRR) as momentous candidates for future photonic crystal integrated circuits (PCICs) draw worldwide attention. In this paper, different configurations are proposed based on single, parallel, and serial PCRRs. To be precise, the different coupling lengths and alignments have been discussed in double and triple PCRRs in parallel and serial configurations to achieve the highest efficiency concerning the desired applications such as an add-drop filter (ADF) and a power splitter. Moreover, in the achieved optimum double and triple PCRRs, the effect of coupling radius change has been discussed.

Remarkably High-Performance Nanosheet GeSn Thin-Film Transistor

High-performance p-type thin-film transistors (pTFTs) are crucial for realizing low-power display-on-panel and monolithic three-dimensional integrated circuits. Unfortunately, it is difficult to achieve a high hole mobility of greater than 10 cm2/V·s, even for SnO TFTs with a unique single-hole band and a small hole effective mass. In this paper, we demonstrate a high-performance GeSn pTFT with a high field-effect hole mobility (μFE), of 41.8 cm2/V·s; a sharp turn-on subthreshold slope (SS), of 311 mV/dec, for low-voltage operation; and a large on-current/off-current (ION/IOFF) value, of 8.9 × 106. This remarkably high ION/IOFF is achieved using an ultra-thin nanosheet GeSn, with a thickness of only 7 nm. Although an even higher hole mobility (103.8 cm2/V·s) was obtained with a thicker GeSn channel, the IOFF increased rapidly and the poor ION/IOFF (75) was unsuitable for transistor applications. The high mobility is due to the small hole effective mass of GeSn, which is supported by first-principles electronic structure calculations.

A Survey on Analog-to-Digital Converter Integrated Circuits for Miniaturized High Resolution Ultrasonic Imaging System

As traditional ultrasonic imaging systems (UIS) are expensive, bulky, and power-consuming, miniaturized and portable UIS have been developed and widely utilized in the biomedical field. The performance of integrated circuits (ICs) in portable UIS obviously affects the effectiveness and quality of ultrasonic imaging. In the ICs for UIS, the analog-to-digital converter (ADC) is used to complete the conversion of the analog echo signal received by the analog front end into digital for further processing by a digital signal processing (DSP) or microcontroller unit (MCU). The accuracy and speed of the ADC determine the precision and efficiency of UIS. Therefore, it is necessary to systematically review and summarize the characteristics of different types of ADCs for UIS, which can provide valuable guidance to design and fabricate high-performance ADC for miniaturized high resolution UIS. In this paper, the architecture and performance of ADC for UIS, including successive approximation register (SAR) ADC, sigma-delta (Σ-∆) ADC, pipelined ADC, and hybrid ADC, have been systematically introduced. In addition, comparisons and discussions of different types of ADCs are presented. Finally, this paper is summarized, and presents the challenges and prospects of ADC ICs for miniaturized high resolution UIS.

Phase Properties of Different HfO2 Polymorphs: A DFT-Based Study

Background: Hafnium Dioxide (HfO2) represents a hopeful material for gate dielectric thin films in the field of semiconductor integrated circuits. For HfO2, several crystal structures are possible, with different properties which can be difficult to describe in detail from an experimental point of view. In this study, a detailed computational approach has been shown to present a complete analysis of four HfO2 polymorphs, outlining the intrinsic properties of each phase on the basis of atomistic displacements. Methods: Density functional theory (DFT) based methods have been used to accurately describe the chemical physical properties of the polymorphs. Corrective Hubbard (U) semi-empirical terms have been added to exchange correlation energy in order to better reproduce the excited-state properties of HfO2 polymorphs. Results: the monoclinic phase resulted in the lowest cohesive energy, while the orthorhombic showed peculiar properties due to its intrinsic ferroelectric behavior. DFT + U methods showed the different responses of the four polymorphs to an applied field, and the orthorhombic phase was the least likely to undergo point defects as oxygen vacancies. Conclusions: The obtained results give a deeper insight into the differences in excited states phenomena in relation to each specific HfO2 polymorph.