Proceedings 29th Annual International Symposium on Computer Architecture ISCA-02
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29

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Using a user-level memory thread for correlation prefetching

Proceedings 29th Annual International Symposium on Computer Architecture ISCA-02 ◽

10.1109/isca.2002.1003576 ◽

2003 ◽

Author(s):

Y. Solihin ◽

Jaejin Lee ◽

J. Torrellas

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Queue pair IP: a hybrid architecture for system area networks

Proceedings 29th Annual International Symposium on Computer Architecture ISCA-02 ◽

10.1109/isca.2002.1003583 ◽

2003 ◽

Author(s):

P. Buonadonna ◽

D. Culler

Keyword(s):

Hybrid Architecture ◽

System Area Networks

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Timekeeping in the memory system: predicting and optimizing memory behavior

Proceedings 29th Annual International Symposium on Computer Architecture ISCA-02 ◽

10.1109/isca.2002.1003579 ◽

2003 ◽

Author(s):

Zhigang Hu ◽

S. Kaxiras ◽

M. Martonosi

Keyword(s):

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Going the distance for TLB prefetching: an application-driven study

Proceedings 29th Annual International Symposium on Computer Architecture ISCA-02 ◽

10.1109/isca.2002.1003578 ◽

2003 ◽

Author(s):

G.B. Kandiraju ◽

A. Sivasubramaniam

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ReVive: cost-effective architectural support for rollback recovery in shared-memory multiprocessors

Proceedings 29th Annual International Symposium on Computer Architecture ISCA-02 ◽

10.1109/isca.2002.1003567 ◽

2003 ◽

Author(s):

M. Prvulovic ◽

Zheng Zhang ◽

J. Torrellas

Keyword(s):

Shared Memory ◽

Cost Effective ◽

Rollback Recovery ◽

Shared Memory Multiprocessors ◽

Architectural Support

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The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays

Proceedings 29th Annual International Symposium on Computer Architecture ISCA-02 ◽

10.1109/isca.2002.1003558 ◽

2003 ◽

Author(s):

M.S. Hrishikesh ◽

N.P. Jouppi ◽

K.I. Farkas ◽

D. Burger ◽

S.W. Keckler ◽

...

Keyword(s):

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Tarantula: a vector extension to the alpha architecture

Proceedings 29th Annual International Symposium on Computer Architecture ISCA-02 ◽

10.1109/isca.2002.1003586 ◽

2003 ◽

Author(s):

R. Espasa ◽

F. Ardanaz ◽

J. Emer ◽

S. Felix ◽

J. Gago ◽

...

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Transient-fault recovery using simultaneous multithreading

Proceedings 29th Annual International Symposium on Computer Architecture ISCA-02 ◽

10.1109/isca.2002.1003565 ◽

2003 ◽

Author(s):

T.N. Vijaykumar ◽

I. Pomeranz ◽

K. Cheng

Keyword(s):

Simultaneous Multithreading ◽

Fault Recovery ◽

Transient Fault

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The optimum pipeline depth for a microprocessor

Proceedings 29th Annual International Symposium on Computer Architecture ISCA-02 ◽

10.1109/isca.2002.1003557 ◽

2003 ◽

Author(s):

A. Hartstein ◽

T.R. Puzak

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SafetyNet: improving the availability of shared memory multiprocessors with global checkpoint/recovery

Proceedings 29th Annual International Symposium on Computer Architecture ISCA-02 ◽

10.1109/isca.2002.1003568 ◽

2003 ◽

Author(s):

D.J. Sorin ◽

M.M.K. Martin ◽

M.D. Hill ◽

D.A. Wood

Keyword(s):

Shared Memory ◽

Shared Memory Multiprocessors ◽

Checkpoint Recovery

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