Learning memory management with C‐Sim: A C‐based visual tool

2019 ◽  
Vol 27 (5) ◽  
pp. 1217-1235
Author(s):  
Baltasar García Perez‐Schofield ◽  
Matías García Rivera ◽  
Francisco Ortin ◽  
María J. Lado
Keyword(s):  
Memory Management ◽  
Visual Tool

Simple, fast, and safe manual memory management

2017 ◽  
Vol 52 (6) ◽  
pp. 233-247
Author(s):  
Piyus Kedia ◽  
Manuel Costa ◽  
Matthew Parkinson ◽  
Kapil Vaswani ◽  
Dimitrios Vytiniotis ◽  
...  
Keyword(s):  
Memory Management

Supporting ada memory management in the iAPX-432

1982 ◽  
Vol 10 (2) ◽  
pp. 117-131 ◽  
Author(s):  
Fred J. Pollack ◽  
George W. Cox ◽  
Dan W. Hammerstrom ◽  
Kevin C. Kahn ◽  
Konrad K. Lai ◽  
...  
Keyword(s):  
Memory Management

Compartmental memory management in a modern web browser

2011 ◽  
Vol 46 (11) ◽  
pp. 119-128 ◽  
Author(s):  
Gregor Wagner ◽  
Andreas Gal ◽  
Christian Wimmer ◽  
Brendan Eich ◽  
Michael Franz
Keyword(s):  
Memory Management ◽  
Web Browser

scholarly journals Real-time FPGA-based implementation of the AKAZE algorithm with nonlinear scale space generation using image partitioning

2021 ◽  
Author(s):  
Parastoo Soleimani ◽  
David W. Capson ◽  
Kin Fun Li
Keyword(s):  
Real Time ◽  
Memory Management ◽  
Scale Space ◽  
Image Resolution ◽  
Hardware Architecture ◽  
Frame Rate ◽  
Time Sharing ◽  
Scale Invariant ◽  
Nonlinear Scale Space ◽  
Nonlinear Scale

AbstractThe first step in a scale invariant image matching system is scale space generation. Nonlinear scale space generation algorithms such as AKAZE, reduce noise and distortion in different scales while retaining the borders and key-points of the image. An FPGA-based hardware architecture for AKAZE nonlinear scale space generation is proposed to speed up this algorithm for real-time applications. The three contributions of this work are (1) mapping the two passes of the AKAZE algorithm onto a hardware architecture that realizes parallel processing of multiple sections, (2) multi-scale line buffers which can be used for different scales, and (3) a time-sharing mechanism in the memory management unit to process multiple sections of the image in parallel. We propose a time-sharing mechanism for memory management to prevent artifacts as a result of separating the process of image partitioning. We also use approximations in the algorithm to make hardware implementation more efficient while maintaining the repeatability of the detection. A frame rate of 304 frames per second for a $$1280 \times 768$$ 1280 × 768 image resolution is achieved which is favorably faster in comparison with other work.

scholarly journals On the Applicability of PEBS based Online Memory Access Tracking for Heterogeneous Memory Management at Scale

2018 ◽  
Author(s):  
Aleix Roca Nonell ◽  
Balazs Gerofi ◽  
Leonardo Bautista-Gomez ◽  
Dominique Martinet ◽  
Vicenç Beltran Querol ◽  
...  
Keyword(s):  
Memory Management ◽  
Memory Access
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