Low complexity iterative decoding of Reed–Solomon convolutional concatenated codes

2021 ◽  
Author(s):  
Ramy Samy ◽  
Ashraf Mahran ◽  
Yahya Mohasseb
Keyword(s):  
Iterative Decoding ◽  
Low Complexity ◽  
Concatenated Codes

Low-Complexity Rate- and Channel-Configurable Concatenated Codes

2020 ◽  
pp. 1-1
Author(s):  
Masoud Barakatain ◽  
Frank R. Kschischang
Keyword(s):  
Low Complexity ◽  
Concatenated Codes

scholarly journals Nonlinear Product Codes and Their Low Complexity Iterative Decoding

ETRI Journal ◽  
2010 ◽  
Vol 32 (4) ◽  
pp. 588-595 ◽  
Author(s):  
Haesik Kim ◽  
Garik Markarian ◽  
Valdemar C. da Rocha, Jr.
Keyword(s):  
Iterative Decoding ◽  
Low Complexity ◽  
Product Codes

A soft-input soft-output APP module for iterative decoding of concatenated codes

1997 ◽  
Vol 1 (1) ◽  
pp. 22-24 ◽  
Author(s):  
S. Benedetto ◽  
D. Divsalar ◽  
G. Montorsi ◽  
F. Pollara
Keyword(s):  
Iterative Decoding ◽  
Concatenated Codes

Hamming Product Code Based Multiple Bit Error Correction Coding Scheme Using Keyboard Scan Based Decoding for on Chip Interconnects Links

2012 ◽  
Vol 241-244 ◽  
pp. 2457-2461 ◽  
Author(s):  
Murali Maheswari ◽  
Gopalakrishnan Seetharaman
Keyword(s):  
Error Correction ◽  
Error Rate ◽  
Iterative Decoding ◽  
Error Control ◽  
Low Complexity ◽  
Hardware Complexity ◽  
Error Correction Coding ◽  
Product Code ◽  
Coding Scheme ◽  
On Chip

In this paper, we present multiple bit error correction coding scheme using extended Hamming product code combined with type II HARQ and keyboard scan based error flipping to correct multiple bit errors for on chip interconnect. The keyboard scan based error flipping reduces the hardware complexity of the decoder compared to the existing three stages iterative decoding method for on chip interconnects. The proposed method of decoding achieves 86% of reduction in area and 23% of reduction in decoder delay with only small increase in residual flit error rate compared to the existing three stage iterative decoding scheme for multiple bit error correction. The proposed code also achieves excellent improvement in residual flit error rate and up to 66% of links power consumption compared to the other error control schemes. The low complexity and excellent residual flit error rate make the proposed code suitable for on chip interconnection links.

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