Hamming Product Code Based Multiple Bit Error Correction Coding Scheme Using Keyboard Scan Based Decoding for on Chip Interconnects Links

2012 ◽  
Vol 241-244 ◽  
pp. 2457-2461 ◽  
Author(s):  
Murali Maheswari ◽  
Gopalakrishnan Seetharaman
Keyword(s):  
Error Correction ◽  
Error Rate ◽  
Iterative Decoding ◽  
Error Control ◽  
Low Complexity ◽  
Hardware Complexity ◽  
Error Correction Coding ◽  
Product Code ◽  
Coding Scheme ◽  
On Chip

In this paper, we present multiple bit error correction coding scheme using extended Hamming product code combined with type II HARQ and keyboard scan based error flipping to correct multiple bit errors for on chip interconnect. The keyboard scan based error flipping reduces the hardware complexity of the decoder compared to the existing three stages iterative decoding method for on chip interconnects. The proposed method of decoding achieves 86% of reduction in area and 23% of reduction in decoder delay with only small increase in residual flit error rate compared to the existing three stage iterative decoding scheme for multiple bit error correction. The proposed code also achieves excellent improvement in residual flit error rate and up to 66% of links power consumption compared to the other error control schemes. The low complexity and excellent residual flit error rate make the proposed code suitable for on chip interconnection links.

scholarly journals Lightweight hamming product code based multiple bit error correction coding scheme using shared resources for on chip interconnects

2020 ◽  
Vol 9 (5) ◽  
pp. 1979-1989
Author(s):  
Asaad Kadhum Chlaab ◽  
Wameedh Nazar Flayyih ◽  
Fakhrul Zaman Rokhani
Keyword(s):  
Power Consumption ◽  
Error Correction ◽  
Error Rate ◽  
Iterative Decoding ◽  
Total Power ◽  
Shared Resources ◽  
Error Correction Coding ◽  
Product Code ◽  
Coding Scheme ◽  
On Chip

In this paper, we present multiple bit error correction coding scheme based on extended Hamming product code combined with type II HARQ using shared resources for on chip interconnect. The shared resources reduce the hardware complexity of the encoder and decoder compared to the existing three stages iterative decoding method for on chip interconnects. The proposed method of decoding achieves 20% and 28% reduction in area and power consumption respectively, with only small increase in decoder delay compared to the existing three stage iterative decoding scheme for multiple bit error correction. The proposed code also achieves excellent improvement in residual flit error rate and up to 58% of total power consumption compared to the other error control schemes. The low complexity and excellent residual flit error rate make the proposed code suitable for on chip interconnection links.

scholarly journals Reliability Analysis of Multibit Error Correcting Coding and Comparison to Hamming Product Code for On-Chip Interconnect

2020 ◽  
Vol 26 (6) ◽  
pp. 94-106
Author(s):  
Asaad Chlab Kadum ◽  
Wameedh Nazar Flayyih ◽  
Fakhrul Zaman Rokhani
Keyword(s):  
Power Consumption ◽  
Error Correction ◽  
Reliability Analysis ◽  
Error Control ◽  
Random Errors ◽  
Product Code ◽  
Coding Schemes ◽  
Control Schemes ◽  
On Chip ◽  
Reduction In Area

Error control schemes became a necessity in network-on-chip (NoC) to improve reliability as the on-chip interconnect errors increase with the continuous shrinking of geometry. Accordingly, many researchers are trying to present multi-bit error correction coding schemes that perform a high error correction capability with the simplest design possible to minimize area and power consumption. A recent work, Multi-bit Error Correcting Coding with Reduced Link Bandwidth (MECCRLB), showed a huge reduction in area and power consumption compared to a well-known scheme, namely, Hamming product code (HPC) with Type-II HARQ. Moreover, the authors showed that the proposed scheme can correct 11 random errors which is considered a high number of errors to be corrected by any scheme used in NoC. The high correction capability with moderate number of check bits along with the reduction in power and area requires further investigation in the accuracy of the reliability model. In this paper, reliability analysis is performed by modeling the residual error probability Presidual which represents the probability of decoder error or failure. New model to estimate Presidual of MECCRLB is derived, validated against simulation, and compared to HPC to assess the capability of MECCRLB. The results show that HPC outperforms MECCRLB from reliability perspective. The former corrects all single and double errors, and fails in 5.18% cases of the triple errors, whereas the latter is found to correct all single errors but fails in 32.5% of double errors and 38.97% of triple errors.  

scholarly journals Fuzzy Based Adaptive Controller for on - Chip Communication

2018 ◽  
Vol 7 (3.27) ◽  
pp. 362
Author(s):  
M Jasmin ◽  
T Vigneswaran
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
Error Detection ◽  
Input Data ◽  
Fuzzy Controller ◽  
Proper Time ◽  
System On Chip ◽  
Coding Scheme ◽  
Error Detection And Correction ◽  
On Chip

Occurrence of bit error is more when communication takes place in System on chip environment. By employing proper error detection and correction codes the bit error rate can be considerably reduced in On-chip communication. As System on chip involves heterogeneous system the efficiency of communication is improved when reconfigurable multiple coding schemes are preferred. Depending upon the requirements for various subsystem the correct code has to be selected. Due to the variations in input demands based on various subsystems the proper selection of codes become fuzzy in nature. In this paper Fuzzy Controller is designed to select the correct coding scheme. Inputs are given to the fuzzy controller based on the application demand of the user. The input parameters are minimum bit error rate, computational complexity and correlation level of the input data. Fuzzy Controller employs three membership functions and 27 rules to select the appropriate coding scheme. The selected coding scheme should be communicated at the proper time to the decoder. To enable the decoding process selected coding scheme is communicated effectively by using less overhead frame format. To verify the functionality of fuzzy controller random input data sets are used for testing.  

Distributed Error Correction Coding Scheme for Low Storage Blockchain Systems

2020 ◽  
Vol 7 (8) ◽  
pp. 7054-7071
Author(s):  
Huihui Wu ◽  
Alexei Ashikhmin ◽  
Xiaodong Wang ◽  
Chong Li ◽  
Sichao Yang ◽  
...  
Keyword(s):  
Error Correction ◽  
Error Correction Coding ◽  
Coding Scheme

scholarly journals A Low-Complexity Ordered Statistics Decoding Algorithm for Short Polar Codes

2019 ◽  
Vol 9 (5) ◽  
pp. 831
Author(s):  
Yusheng Xing ◽  
Guofang Tu
Keyword(s):  
Error Correction ◽  
Error Rate ◽  
Complexity Analysis ◽  
Signal To Noise Ratio ◽  
Low Complexity ◽  
High Signal ◽  
Polar Codes ◽  
Decoding Algorithm ◽  
Low Snr ◽  
Ordered Statistics

In this paper, we propose a low-complexity ordered statistics decoding (OSD) algorithm called threshold-based OSD (TH-OSD) that uses a threshold on the discrepancy of the candidate codewords to speed up the decoding of short polar codes. To determine the threshold, we use the probability distribution of the discrepancy value of the maximal likelihood codeword with a predefined parameter controlling the trade-off between the error correction performance and the decoding complexity. We also derive an upper-bound of the word error rate (WER) for the proposed algorithm. The complexity analysis shows that our algorithm is faster than the conventional successive cancellation (SC) decoding algorithm in mid-to-high signal-to-noise ratio (SNR) situations and much faster than the SC list (SCL) decoding algorithm. Our addition of a list approach to our proposed algorithm further narrows the error correction performance gap between our TH-OSD and OSD. Our simulation results show that, with appropriate thresholds, our proposed algorithm achieves performance close to OSD’s while testing significantly fewer codewords than OSD, especially with low SNR values. Even a small list is sufficient for TH-OSD to match OSD’s error rate in short-code scenarios. The algorithm can be easily extended to longer code lengths.

scholarly journals Adaptive Multibit Crosstalk-Aware Error Control Coding Scheme for On-Chip Communication

2016 ◽  
Vol 63 (2) ◽  
pp. 166-170 ◽  
Author(s):  
Wameedh Nazar Flayyih ◽  
Khairulmizam Samsudin ◽  
Shaiful Jahari Hashim ◽  
Yehea I. Ismail ◽  
Fakhrul Zaman Rokhani
Keyword(s):  
Error Control ◽  
Error Control Coding ◽  
Coding Scheme ◽  
On Chip

Error Correction Based on LDPC Codes in Wireless Optical Communication

2013 ◽  
Vol 380-384 ◽  
pp. 3811-3814
Author(s):  
Xiao Rong Gao ◽  
Pei Wang ◽  
Jian Qiang Guo ◽  
Jin Long Li ◽  
Kai Yang ◽  
...  
Keyword(s):  
Error Correction ◽  
Optical Communication ◽  
Error Rate ◽  
Error Control ◽  
Channel Model ◽  
Ldpc Codes ◽  
Atmospheric Environment ◽  
Atmospheric Scattering ◽  
Wireless Optical Communication ◽  
Beam Expander

Complex atmospheric environment seriously affect the quality of wireless of information transmission. In order to improve the wireless optical communication quality, and reduce the influence of attenuation, flicker, angle misalignment caused by atmospheric scattering, absorption, turbulence, beam expander, mismatch, atmospheric channel model is established while coding techniques for error control in wireless optical communication was researched into.The improvement result of error rate by error correction coding in different SNR situations was obtained. The results showed that the LDPC coding can significantly reduce the BER. For Gaussian channel, SNR can be reduced 8 dB when BER is 10-6; For wireless optical communication , LDPC codes can make the error rate reduced by 4-5 orders of magnitude.

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