A Design and Implementation of Reconfigurable Architecture for Neural Networks Based on Systolic Arrays

2006 ◽  
pp. 1328-1333 ◽  
Author(s):  
Qin Wang ◽  
Ang Li ◽  
Zhancai Li ◽  
Yong Wan
Keyword(s):  
Neural Networks ◽  
Reconfigurable Architecture ◽  
Systolic Arrays ◽  
Design And Implementation

RiSA: A Reinforced Systolic Array for Depthwise Convolutions and Embedded Tensor Reshaping

2021 ◽  
Vol 20 (5s) ◽  
pp. 1-20
Author(s):  
Hyungmin Cho
Keyword(s):  
Neural Networks ◽  
Convolutional Neural Networks ◽  
Language Processing ◽  
Systolic Array ◽  
Data Reuse ◽  
Systolic Arrays ◽  
High Data ◽  
Area Efficiency ◽  
High Area ◽  
Accelerator Design

Depthwise convolutions are widely used in convolutional neural networks (CNNs) targeting mobile and embedded systems. Depthwise convolution layers reduce the computation loads and the number of parameters compared to the conventional convolution layers. Many deep neural network (DNN) accelerators adopt an architecture that exploits the high data-reuse factor of DNN computations, such as a systolic array. However, depthwise convolutions have low data-reuse factor and under-utilize the processing elements (PEs) in systolic arrays. In this paper, we present a DNN accelerator design called RiSA, which provides a novel mechanism that boosts the PE utilization for depthwise convolutions on a systolic array with minimal overheads. In addition, the PEs in systolic arrays can be efficiently used only if the data items ( tensors ) are arranged in the desired layout. Typical DNN accelerators provide various types of PE interconnects or additional modules to flexibly rearrange the data items and manage data movements during DNN computations. RiSA provides a lightweight set of tensor management tasks within the PE array itself that eliminates the need for an additional module for tensor reshaping tasks. Using this embedded tensor reshaping, RiSA supports various DNN models, including convolutional neural networks and natural language processing models while maintaining a high area efficiency. Compared to Eyeriss v2, RiSA improves the area and energy efficiency for MobileNet-V1 inference by 1.91× and 1.31×, respectively.

An Efficient Parallel Yet Pipelined Reconfigurable Architecture for M-PLN Weightless Neural Networks

2014 ◽  
Author(s):  
Felipe P. da Silva ◽  
Alan Oliveria de Sá ◽  
Nadia Nedjah ◽  
Luiza de Macedo Mourelle
Keyword(s):  
Neural Networks ◽  
Reconfigurable Architecture

Design and implementation of an adapative single pole autoreclosure technique for transmission lines using artificial neural networks

1996 ◽  
Vol 11 (2) ◽  
pp. 748-756 ◽  
Author(s):  
D.S. Fitton ◽  
R.W. Dunn ◽  
R.K. Aggarwal ◽  
A.T. Johns ◽  
A. Bennett
Keyword(s):  
Neural Networks ◽  
Artificial Neural Networks ◽  
Transmission Lines ◽  
Design And Implementation ◽  
Artificial Neural

Design and implementation of a self-tuning control using artificial neural networks of second order

2006 ◽  
Author(s):  
Mario Ibarra-manzano ◽  
Dora Almanza-ojeda ◽  
Andres Hernandez-Gutierrez ◽  
Juan Amezquita-sanchez ◽  
Luis Lopez-martinez
Keyword(s):  
Neural Networks ◽  
Artificial Neural Networks ◽  
Second Order ◽  
Design And Implementation ◽  
Self Tuning ◽  
Artificial Neural
Sign in / Sign up

Export Citation Format

Share Document